PDP-8/I memory problem

From: O. Sharp <ohh_at_drizzle.com>
Date: Wed Nov 5 14:32:10 2003

I finally got the original post, along with the followup. :)

It suddenly dawned on me that I've got the memory-extension schematics
on my hard drive (thank you, Mr. Kossow!), and can actually look at
them without digging through the storage room...

In the Memory Extension Control the MB is indeed buffered, and becomes
the MCBMB (presumably "Memory-Control-Buffered Memory Buffer").
Curiously, it rebuffers the MB by taking the signal from the _other_
side of the original MB00 flip-flop - e.g., MB00(1) - and inverting
it prior to use. I'm guessing this is to minimize rewiring of the
backplane when installing the extended-memory option. The inversion
for MB00 takes place on the M617 at B12. Does the problem move down to
MB06 if you swap the M617s at B12 and B13? Similarly, is the MB00(1)
signal making it from E34 pin T2 to B12 pin A1?

I don't know if that'll make a difference, but I'm hoping. :) The
rebuffering looks like it's primarily for extensions located off the
main board, but it may affect the first two 4K stacks as well.. I'm
not sure what wiring changes, if any, are done on the 8/I backplane to
accomodate the memory-extension control, or whether the MB/MCBMB
signals are a part of that. Anyone know of a reference for this?

Anyway, that's my thought. I hope it helps, because if that isn't it
the guesses start getting esoteric. :) :)

                       -O.-
Received on Wed Nov 05 2003 - 14:32:10 GMT