Multi-CPU Qbus VAXen

From: Steven M Jones <>
Date: Wed Oct 8 16:38:48 2003

emanuel stiebler wrote:
> Check the note again. AFAIRC, this (ka630, ka650, ...) had just a
> "mailbox" register to communicate, and only one cpu had access to the
> qbus. The other ones had the qbus interface shut down. So, if you didn't
> have you special backplane with 4 qbuses, it was pretty limited ...

While the note doesn't describe how, it does indicate you have to
reconfigure the auxiliary processors. Things like disabling the TOY
clock, the bus arbiter logic, setting the address of the Interprocessor
Communications Register (ICR, the "mailbox" you referred to).

You can however do this in regular backplanes. Okay okay, you may
want to make sure you use a BA11-S since it's Q22 and all Q/CD slots.
The common BA23/123 backplanes would be pretty short on Q/CD slots for
more than two processors unless you don't need memory for them... And
then the bus termination would get pretty funky, too.

Eric Smith wrote:
> The resulting system does not have shared memory (except for any
> Qbus memory), so it isn't generally suitable for operating systems
> that support SMP. That's one reason why DEC never officially
> supported such configurations.

This is one reason I thought of V, a message passing OS (unless my
memory is faulty). My papers are all in a box somewhere, but it dated
from the early to mid 80's at Stanford, and I'm pretty sure it ran on

While there are plenty of applications where UMA is handy, necessary,
or essential, there are cases where it isn't. I'm sure somebody used
the feature, or it never would have been put in silicon. When I
thought about the 3520/3540 I wondered if they used these features
with redesigned CPU boards to provide a different memory interconnect
but take advantage of the ICR etc.

Received on Wed Oct 08 2003 - 16:38:48 BST

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