brew-your-own-unibus boards?

From: Peter C. Wallace <pcw_at_mesanet.com>
Date: Tue Jan 20 13:54:39 2004

On Tue, 20 Jan 2004, der Mouse wrote:

> > For me, at least, the hard part of designing a modern Qbus and/or
> > Unibus interface would be what to select for bus drivers.
>
> Well, for Qbus...there's an appendix in the KA630 document that's
> titled "Q22-Bus Specification". Based on that:
>
> >From the looks of it, for a driver you can use almost any
> open-collector TTL output - at least, a quick look at the specs doesn't
> reveal anything that stands out as incompatible.
>
> The receivers are a bit more interesting. The spec says that their
> threshold must be between 1.3 and 1.7 volts and that their high-level
> input current must be no greater than 80µA; it fails to give any limits
> on how much current they source into a low-level input, though there
> surely must be such a limit. Are there any bus receiver chips that
> have a reference-voltage pin, which could be connected to (say) 1.5V?
> Basically, a bunch of specialized voltage comparators?
>
> Personally, I'd be tempted to just use TTL and see if it works (LSTTL,
> probably, since that sources less current into low-level inputs). But
> of course "it works for me" isn't good enough if you're designing for
> other people's use.
>
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Well here is what I would do:

        Use 34C86 line receivers as inputs - these also have the advantage of
having hysteresis and meeting the low input current at 0 VCC spec. You do get
about 20 ns of propagation delay but that should be ok. There are faster parts
available if need be. The - inputs of the line receivers would be connected to
the desired threshold.

        For drivers, I would use small (SOT23) discrete Mosfets perhaps with a
small (10 Ohm?) drain resistor to avoid damage if inadvertantly shorted to 5V.
The gate drive could be RC slew limited to keep the output edge rate within
reason.

        For the bus state machine logic, I would use a small FPGA say a
XC2S50E-TQ144 (~$12 is low quantities) This would also have enough BlockRAM to
present 1KX16 to the QBUS as a boot ROM (is this enough?) and also 1KX16 to
the local processor for booting. I would use a standard serial flash for
downloading the FPGA config and firmware storage. A 8Mbit serial flash costs
about $2.25. Most of this space is free so the local processor can load its
RAM from the serial flash (about 900K bytes available) for its MSCP code. For
as local processor I would probably use a AMD AU1500 (about $26 for the
slowest speed grade, IIRC has serial port, AC97 codec interface for audio, 2
100BT Ethernet, 2 USB ports, SDRAM interface for say 16M SDRAM (about $6.00)
and PCI bus. The PCI bus would connect to the IDE controller chip (not sure
which to use and price) and perhaps have an expansion slot or two (MiniPCI-3
perhaps - they are low enough to fit)


        We pay about $.35 per square inch for 4 layer PCBs so with gold I
would guess PCB would be in the ~$20.00 range.

Peter Wallace
Received on Tue Jan 20 2004 - 13:54:39 GMT