SV: Looking for a device programmer that doesn't require Weendoze

From: Paul Koning <>
Date: Sun Mar 21 15:26:41 2004

>>>>> "Ulf" == Ulf Andersson <> writes:

>> Paul Koning wrote:
>> But the real issue is that NO ONE will tell you the internals of
>> their FPGA, so you can't figure out the bit patterns that you need
>> to perform a given logic function. Too bad really, because the
>> logic synthesis software available from the chip vendors often
>> sucks pretty badly. I have a bunch of battle scars coping with
>> really stupid bugs in Lattice tools, which will not be fixed since
>> they are apparently considered normal behavior.
>> I think if you have infinite pull the situation is sometimes
>> better -- I've seen some evidence that DEC was able to get Xilinx
>> to tell it how to synthesize for those chips. And they did it
>> much better... but those were research tools in the Palo Alto
>> group only.
 Ulf> Oh, they do tell you, but for a substantial fee, and an NDA to
 Ulf> go with that, just to make shure they can sue your pants off
 Ulf> when you happen to spill the secret... :)

 Ulf> There is rumor of a Verilog simulator/synthesiser that speaks
 Ulf> Xilinx. I have not yet tried it but here is the link:


 Ulf> It is for free and as such it might suck, but at least it do
 Ulf> that for a moderate fee.

Cool. But I was talking about the place & route and programming bit
pattern generators. Those are still deep secrets.

Place and route is the one that I find myself fighting with. Things
like: (a) run a synthesis, with pins unlocked. (b) just to check
things, run the exact same design with the pins locked to what (a)
chose. Result: synthesis fails, not enough room. #&_at_$*(#@* so how
is a person supposed to create a design that can be tweaked and still
work on the same PCB layout?

Answer: this is normal. Gronk. I guess it's a trick to make you buy
bigger FPGAs...

Received on Sun Mar 21 2004 - 15:26:41 GMT

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