DEC RK07 drive interface specs wanted

From: Brad Parker <>
Date: Fri May 14 08:04:48 2004

Paul Koning wrote:
>.... Again, a software emulation may not get there in time.

Yes, agreed. My plan was to be able to have the cpld "hold off" the
unibus cpu until the micro could "get there in time" in the cases where
that was needed. This is the heart of the shared-register-file-interlock

>You might try to cheat by holding off SSYN on the Unibus read until
>any pending CSR fixups are done, but then the microcontroller has a
>rather tight time limit (20 microseconds or so).

:-) as Homer Simpson says, "good idea, boss!"

My plan is to try and make that work. 20us is not a huge amount of time
but it is in the relm of the possible. Off the cuff I'd say it would be
tight for a 40mhz pic; it might be easier on an ARM7 with an fiq
interrupt. I plan to simulate the unibus hdl, figure out the window and
plan the micro and it's code around that window.

Received on Fri May 14 2004 - 08:04:48 BST

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