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Date: Sun Feb 27 13:35:59 2005

"U517 and U516 are PROMs which decode the latched address lines and
determine which memory chips are to be enabled. Specifically, U517
determines which of the eight 8K banks is to be enabled, and U516 determines
which of the 1k pages within bank 0 is to be enabled. However, the address
lines are not the only criteria used to determine memory selection.

"Jumpers JJ501, JJ502, JJ503, and JJ504 select various memory
configurations. That is, if only 16k of user RAM is installed, then JJ501,
JJ502, and JJ504 [that's a typo, I think it should say JJ503] are jumpered
for 0 and JJ504 is a "don't care". As a result, only RAS0 L will be selected
(coincident with the selected address being within banks 1 and 2). At no
time will RAS1 and RAS2 be selected. In addition, NOMEM L will be asserted
low whenever banks 3, 4, 5, 6, or 7 are accessed. This results in U521 being
enabled and all 0's being forced onto the data bus (required by some softare
memory sizing routines). If however, 32k of user memory is installed, JJ501
and JJ503 will be jumpered for 0 and JJ502 jumpered for a 1. JJ504 is again
a "don't care". Now, when banks 3 and 4 are addressed, RAS1 L will be
asserted instead of NOMEM L, while RAS0 L requires the same conditions as

"The write enable line (WE L) will be asserted low whenever there is no read
(BRD L is high), no refresh (BRSH L is high), memory is selected (DMERQ L is
low), and the bank selected contains writeable memory. This, since NOMEM L
contains no writeable memory, WE L cannot be asserted if NOMEM L is
asserted. However, bank 0 contains both writeable and non-writeable memory.
Therefore WE L will be asserted for bank 0 if the first three conditions are
met regardless of the fourth condition. It is up to U516 to either enable or
not enable the page select lines (MC5001 L, MC5023 L, MC505 L, and MC5067
L), depending on whether the memory addressed is writable or not.

"Write enable line 0 (WE 0 L) is used with the 1k of RAM associated with the
floppy disk. It is only asserted when WE L is asserted, MC505 L is asserted,
and FMWEN H is asserted. It is controlled by bit 7 of I/O port 177.

"If the refresh line (BRFSH L) is asserted low, then WE L is not asserted.
In addition, RAS0 L, RAS1 L, and RAS2 L will be asserted (consistent with
the position of jumpers JJ501, JJ502, JJ503, and JJ504) regardless of the
bank address. This ensures that all applicable dynamic RAM will be

"U518 is the system ROM which resides in the bottom 2 pages of memory (0,
1). An additional 2k of ROM can be added to the system at Pages 2 and 3 by
installing jumper JJ508 at "A". Jumpers JJ505, JJ506, and JJ507 are used to
switch between the 3-voltage EPROMS and single-voltage ROMs. When the
jumpers are installed in their 0 locations, then the 3-voltage EPROMs are

"U520 is the floppy disk ROM which resides in the address map at pages 6 and
7. It is restricted to a single voltage ROM. However, by moving jumper JJ508
to 'B', U519 will serve as the floppy ROM and a 3-voltage EPROM can be
installed. It is now no longer possible to use 4k of system ROM.

"U550 is a 256x8 PROM, and decodes the various I/O ports required by the
Computer. I/O 362L is the general purpose port. IO NMI L is used by the
system to trap all accesses to ports 360, 361, 372, and 373. This enables
the system to run previous software developed for the H8 Computer. That is,
accesses to the H8 front panel are rerouted to the system console.

The jumper configurations are given as follows:

   MEMORY JJ504 JJ503 JJ502 JJ501
   16K B 0 0 0
   32K B 0 0 1
   48K B 0 1 0

On U517, JJ501-503 are wired directly to A5-7 inputs respectively. Input A4
is wired to BRD L, and A3 is wired to BRFSH L. Inputs A0-2 are wired to CPU
address lines A13-15 respectively. On the output side of this PROM, bit 0
is wired to one of U516's two CS lines; bit 1 is wired to U521 so it appears
to be the NOMEM L signal referred to above; bit 2 is RAS0 to onboard DRAMs;
bit 3 is RAS1 to onboard DRAMs; bit 4 is RAS2 if JJ504 is in position B,
otherwise RAS at the DRAMs U542-9 is pulled high by RP506 and the bit 4
output of the PROM appears on pin 18 of connectors P507-509 and is
designated "RD5"; bit 5 appears at pin 19 of connectors P507-509 and
designated "RD6"; bit 6 appears at pin 20 of connectors P507-509 and is
designated "RD7"; and bit 7 is WE to onboard DRAM U526-549, and the unused
static RAM sockets U522 and U524.

What I don't see in the schematic is any connection between the I/O port
mapping PROM U550 and the address decode PROMs, so the map doesn't appear to
be in any way software-controllable. So did Heath choose to remap RAM to
start at 0000h in later PROMs and just modify HDOS to accomodate? If that's
true, what's getting the Z80 reset to start from the correct location?

Tony, if you have dumps of U516 and U517, would you mind making those
available? Also, I have several revisions of each of these that I'd like to
dump. How did you dump them? FWIW all of the boards I have have 444-66
(U517) and 444-83 (U516) and 444-61 (U550), except one spare, which is
missing U517 and has U516=444-41 and U550=444-43.

Dwight, Tony may have dumps of U518 (the MTR EPROM) as well, but if not, I
can easily provide those in versions 444-40 (is that MTR-88?), 444-62
(MTR-89) and 444-142 (MTR-90 48/96TPI). I don't seem to have 444-84 (MTR-90
48TPI only). I can also provide a dump of U520.

Received on Sun Feb 27 2005 - 13:35:59 GMT

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