PDP-11 addressing question and a model round-up

From: Paul Koning <pkoning_at_equallogic.com>
Date: Mon Feb 14 14:34:47 2005

>>>>> "Tom" == Tom Jennings <tomj_at_wps.com> writes:

>> On Mon, 14 Feb 2005, Paul Koning wrote:
>>> With MMU enabled, each 4 kW chunk of program address space is
>>> mapped to a physical address of your choice (possibly two
>>> separate ones, in MMUs that support separate instruction and data
>>> space maps).

 Tom> Just FYI, Data General's method is pretty much the same; it's a
 Tom> standard technique. DG maps the 15-bit user space (16 bit words)
 Tom> in 4K chunks into physical memory. There is a separate map, in
 Tom> 256 word chunks, for memory protection eg. read-only, for
 Tom> example shared binary (unix "text") or OS overhead.

 Tom> IO is fairly primitive on DGs, though pretty nice and very
 Tom> simple. Other than MUL and DIV &c mapped programs error-trap on
 Tom> IO instructions.

 Tom> There's also a data channel, aka DMA. The Novas are not fast,
 Tom> one motorcycle (megacycle (OK, megaHertz)) or so, but the
 Tom> Supernova allows data channel to start up mid-instruction!

Same for PDP-11s.

The resemblance isn't all that surprising if you consider that DG was
founded by DEC people whose design ("PDP-X" -- see Al's scans) for a
PDP-8 successor was rejected. So they built the Nova (and DEC build
the PDP-11).

Received on Mon Feb 14 2005 - 14:34:47 GMT

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