HDL vs. schematics (was Re: ebay - cardamatic)

From: Eric Smith <eric_at_brouhaha.com>
Date: Wed Feb 16 19:28:35 2005

I wrote (about FPGAs):
> I strongly disagree. The hardware carry chain is a Very Good Thing,
> not a cheat. Certainly it doesn't solve all problems, but in terms
> of value for the amount of extra silicon it requires, it's extremely
> cost effective.

woodelf wrote:
> I say it is a cheat because if you impliment carry logic and the software
> decides to use the hardware carry chain you don't really know the real
> timing of your design.

Certainly you do. It's in the post-PAR (place and route) timing
report. That's the only way you can know what the timing will be,
whether it uses the carry chain or not. The individual logic
elements have easily predictable timing, but routing does not and
has a huge influence on the circuit speed.

> Using altera 10K FPGA software that has
> a similar carry chain many years ago, I found when I got to 80%
> of the resources the cycle time really got long.

I don't see how use of the carry chain can slow anything down. The
only problem you run into is if you expect to use the carry chain,
and the router is unable to do so, which is possible if the utilization
is very high. In that case, you put in some constraints for force
it to use the carry chain, or to pin down the adder bits to specific
places. I've done designs with >90% utilization of logic cells and
have never had to do that to get the carry chains to be routed
properly.

> Not directy , but you often see XYZ RISC machine has a ABC cycle time.
> Most of the speed is because of the block ram and fast carry of Xilinix
> chips.

And since that's a benchmark of a processor, that's entirely reasonable
since most processors are going to use the carry chain and block RAMs.
It doesn't tell you how fast something other than a processor is, nor
do they claim it does. You're trying to read too much into one
benchmark.

> 90 macro-cells the amtel CPLD's were cheaper ( 5Volt logic - 128 cells )
> than Xilinx chose them.

Yes, the Xilinx 5V stuff is more expensive. I don't use any 5V CPLDs
or FPGAs. I either use 3.3V stuff that has 5V tolerant inputs, or
use 3.3V parts with 74LVCxxx buffers which are 5V tolerant.

An XC95144XL has 144 macrocells, 5V tolerant I/O, and costs under $7
in quantity one. Unless you have to drive strict 5V CMOS inputs, it
will work fine with any 5V logic. For the price savings you can
easily afford the 3.3V regulator.

Eric
Received on Wed Feb 16 2005 - 19:28:35 GMT