RTL Logic

From: Steve Thatcher <melamy_at_earthlink.net>
Date: Fri Jan 7 15:46:31 2005

I did wired-and with open collector TTL gates all the time... common as dirt! LOL

-----Original Message-----
From: Tom Jennings <tomj_at_wps.com>
Sent: Jan 7, 2005 3:59 PM
To: Steve Thatcher <melamy_at_earthlink.net>,
        "General Discussion: On-Topic and Off-Topic Posts" <cctalk_at_classiccmp.org>
Subject: RE: RTL Logic

On Fri, 7 Jan 2005, Steve Thatcher wrote:

> dirt has been known to be found in most places in the world...
> doing a wired-or and wired-and depends on reading IC specifications for specific chips. It is what design engineers do...

Sorry for being so obtuse! Phrase meant: "wire OR/etc was very
common in RTL".

I tried wired-OR once in TTL, didn't like the results :-)

> -----Original Message-----
> From: Tom Jennings <tomj_at_wps.com>
> It varies from chip to chip and family to family. Wire OR/etc was
> common as dirt.
Received on Fri Jan 07 2005 - 15:46:31 GMT

This archive was generated by hypermail 2.3.0 : Fri Oct 10 2014 - 23:37:43 BST