ISA bus hack

From: Jim Battle <>
Date: Mon Jan 31 17:04:50 2005

Mentioning my old employer, Calera Recognition Systems, reminded me of
this ISA bus "hack."

The OCR accelerator cards that Calera sold were able to find a free
space in the memory map of the ISA bus and could even support multiple
cards on one bus. No flash, jumpers, or dipswitches were involved, and
this was before any Plug and Play.

How it worked was this. The cards had a 68020 on them, along with a
couple megabytes of memory and a few ASICs that accelerated key parts of
the OCR algorithm. The 68020 would wake up from reset and "spin" --
meaning it would program a control register to indicate what address it
was located at. It would park there for a while waiting to get written
to by the host x86. If it didn't receive a write, it would move to the
next address range, etc, and go around again and again util it was told
to stay put.

Complicating all of this was that the card very well might map to an
address where some other card or memory already lived. The OCR card, in
this mode, did not drive any signals, and was able to handle to 0 wait
state writes. If the x86 was writing to or reading from RAM where the
card was also located, the 68020 would see these and ignore them unless
they followed a very complicated asymptotically approaching 0
probability sequence such that a card, seeing the sequence, was certain
that it was the x86 trying to talk to it. Once a card received the
sequence and was told to become visible, it would then turn on any
handshake logic and could respond to reads and writes.

The next layer of the onion was that multiple cards could be in the
system at the same time. You don't want two cards to "wake up" at the
same address in memory and then have a tristate catfight. Instead, part
of the wake up sequence involved a one bit at a time arbitrartion
process based on the card's unique serial numbers.

Finally, the memory system attached to the 68020 wasn't fast enough to
receive the reads and writes with zero wait state performance. However,
the reset and interrupt request logic was, so that is what was used to
signal to the 68020. The magic sequence of writes was seen on the 68020
as a sequence of interrupts and resets that followed a certain pattern
(the logic could tell apart a hard reset from a soft reset; we were
worried that the 68020's internal state wouldn't persist through soft
reset, so we used a register that was inside one of the ASICs that was
known to not get reset to hold the required tracking state).

Parts of the implementation were overly complicated due to the fact that
none of it was designed up front. It was implemented after we realized
that we really didn't need to use the dip switches.

Although it was all stochastic, all of the shenanigans would typically
take less than a second so that nobody really noticed, and not having
dip switches made the card a snap to install.
Received on Mon Jan 31 2005 - 17:04:50 GMT

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