Replies to various threads

From: Allison J Parent <>
Date: Thu Apr 23 09:35:30 1998

<The PDP-11 architecture has only 7 GP registers (since you can't really u
<the PC for just anything) but that's good for the times, and they really

Really, you can do things to the PC that most micros don't even have
instructions for. there are four addressing modes of not for the PC
immediate, absolute, relative and relative defered which when applied
to a any other register are autoincrement, autoincrement defered,
indexed and indexed defered. That distinction is quite powerful and
only some of that is available in many micros and generally distinct
instructions. Most micros have a data follows instruction (immediate)
and an address follows instruction (absolute) but the other two are
far less commonly implemented.

The biggest non-risc is the addressing modes some are impossible for most
risc machines. The two operand addresses uncommon to RISC and most
micros. Add to it the defered mode (register contains the address of
a word in ram that contains the address of an operand). That impacts
compiler complexity and code density.

<And of course it loses on the microcode vs hardware decode.

Oops. The chip versions are microcoded as was the 11/60 but I believe
the 11/05 and 11/20 were hardware decode.

Received on Thu Apr 23 1998 - 09:35:30 BST

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