Replies to various threads

From: Allison J Parent <>
Date: Thu Apr 23 22:37:19 1998

<> Compared to maybe 6800 or 6502, the 8080 had 4 16bit registers (bc, de,
<> hl, sp). The z80 added a second set and IX/IY. But that was only one
<> aspect.
<Oh come on. The 16 bit registers in the Z80 were hardly general-purpose
<in the PDP11 or RISC sense. HL was almost a 16 bit accumulator.

My comment was to point out that most of the micros were not register
poor like the 6800 or 6502 only that they really didn't use them well.

<The ARM was developed as a 32 bit replacement for the 6502 according to
<one rumour (from Acorn, BTW). They didn't like any of the existing 16 or
<32 bit chips, so they designed their own...

I've looked briefly at that chip and it's real simple and straightforward.
Never had a chance to play with one.

<The one instruction per clock cycle definition is daft IMHO. It shouldn't
<matter whether you take a 64MHz clock and have 8 cycles per instruction
<or take an 8MHz clock and derrive other timing signals from it using gate
<delays or a delay line. The throughput is the same. And the critical
<paths have the same timing.

I agree mostly save for at the time that notion was in vogue the maximum
clock rate was circuit limited in NMOS and CMOS devices so fewer clocks
for a cycle equaled greater speed. Most of the RISC proponents of the
time were talking lower transistor counts, clock frequencies, lower
silicon cost and higher testability than their CISC counterparts for the
same overall system performance. The concept was really applicable to
microprocessors as no engineer at the time could even conceive of
injecting clock at 100mhz in to a micro at a time when gate propagation
delays at the silicon level were greater than 10ns. The concept was
appealing when z80s were hitting the wall at 6mhz and 8086s were fast at
10mhz. Of course as Hmos-III and sub 1micron CMOS started to show signs
of going much faster...

Received on Thu Apr 23 1998 - 22:37:19 BST

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