front panels

From: Allison J Parent <allisonp_at_world.std.com>
Date: Tue Feb 24 11:49:55 1998

<But surely this is a limitation of the front panel not the processor.
<I/O bus cycles can (easily) be generated from an appropriately designed
<front panel.

Processor. The 8080 CPU does I/O To/From the accumulator which is
inaccessable from the front pannel being an internal register. An altair
did things by forcing a jump(C3h, xx, zz) the address switches were used
as zzxx forcing the PC to take the set value. Data at a given MEMORY
address was displayed as a result of the current address and stopping
before the next instructing fetch. Writing to MEMORY was simply gating
the data switches and forcing a write pulse (no cpu execution). Its
design was to allow insetion of code into memory and examination of
memory as those were direct. IO however while it would be nice to
interogate or write to devices could leave the cpu "out of sync" since
all IO is done from the accumulator. To do that you really need a soft
front panel and once you do that, displaying or altering the Acc, BC, DE,
HL and SP registers and associated flags are possible.

Did my fair share of 8080/8085/z80 designs in the '70s.

Allison
Received on Tue Feb 24 1998 - 11:49:55 GMT