front panels

From: Yowza! <yowza_at_yowza.com>
Date: Tue Feb 24 13:06:57 1998

On Tue, 24 Feb 1998, Allison J Parent wrote:

> <But surely this is a limitation of the front panel not the processor.
> <I/O bus cycles can (easily) be generated from an appropriately designed
> <front panel.
>
> Processor. The 8080 CPU does I/O To/From the accumulator which is
> inaccessable from the front pannel being an internal register. An altair
> did things by forcing a jump(C3h, xx, zz) the address switches were used
> as zzxx forcing the PC to take the set value. Data at a given MEMORY
> address was displayed as a result of the current address and stopping
> before the next instructing fetch. Writing to MEMORY was simply gating
> the data switches and forcing a write pulse (no cpu execution). Its
> design was to allow insetion of code into memory and examination of
> memory as those were direct. IO however while it would be nice to
> interogate or write to devices could leave the cpu "out of sync" since
> all IO is done from the accumulator. To do that you really need a soft
> front panel and once you do that, displaying or altering the Acc, BC, DE,
> HL and SP registers and associated flags are possible.
>
> Did my fair share of 8080/8085/z80 designs in the '70s.

But what does an instruction do? It just generates bus cycles, right?
The bus doesn't care whether those cycles come from the CPU or something
else (unless there's bus mastering and arbitration, which I doubt).

The difference between generating a memory cycle and and I/O cycle on an
Intel CPU is simply a matter of clocking a different value onto the
"control bus" (which might be a multiplexed bus, I don't know the 8080
that well).

-- Doug
Received on Tue Feb 24 1998 - 13:06:57 GMT