VUPs to MIPS to microcode

From: Captain Napalm <>
Date: Fri Jan 9 01:06:51 1998

It was thus said that the Great Tony Duell once stated:

Someone said:

> take many clock cycles. RISC by definition is at most two clock cycles
> to execute a given instruction. Generally RISC machines can perform

Tony Duell then replied:
> I'm not that well up in modern processor design, but I've never heard of
> that definition. In fact the ARM becomes CISC by it, I think (?).

Then Allison J Parent replied:

> That was part of the mid 80s def, but by no means an exclusive item.

There really isn't a single concensus as to what RISC really means, other
than Reduced Instruction Set Computer (and CISC - Complex Instruction Set
Computer) although there typically are conventions.

  The RISC concept came out of R&D by IBM (notably. I think Stanford was
also doing research into this). They were studying the instructions used by
compilers and noted that typical compilers only used the simpler
instructions and addressing modes, since compilers then weren't
sophisticated enough to use the more complex instructions (or it was harder
to map the complex instructions into what the compiler was compiling). IBM
reasoned that it would be better to make a CPU with only those instructions
commonly used, with simple addressing modes. This would make the CPU easier
to build and test. And a simpler design is easier to speed up.

  IBM produced the RS (I think - memory is going) line of computers which
were the first commercial available system based upon the RISC ideal. Note
that it didn't have some of the traits to later come out of RISC like
pipelines or fixed length instructions.

  Later on, any complexity lost to instructions was later gained by
pipelining, caching, branch prediction and other esoteric stuff.

> Anyway, what's a clock cycle? The PERQ executes one microcycle per clock
> input cycle _but_ there's a few dozen other timing signals that fly about
> the CPU board that are produced by feeding the master clock into a delay
> line and combining the outputs from the taps of said delay line. An
> alternative design would have been to use a much faster master clock and
> divide it down using counters/shift registers. Are you saying that (had
> the microcycle == 1 instruction cycle) the first would have been RISC but
> the second CISC, where the 2 machines would execute the same instruction
> set at the same real speed. If so, the terms RISC and CISC are totally bogus.

  Well, most RISC computers are hardpressed to execute an instruction in a
single clock cycle. For instance, a RISC CPU may take four cycles to
execute a single instruction, say, fetch, decode, execution and store. But
by using a pipeline, these four stages (for example) can be overlapped so
that at any given cycle, there are four instructions in various parts of
being executed.

  Like I said, the criteria of RISC and CISC are rather arbitrary, but the
convention is that you have a simple regular instruction set and only one or
two addressing modes (with most operations being between registers).


> The ARM used more clocks but not many. The early defininition was simply
> Reduced Instruction Set and raw speed to make up for it. A PDP-8 would
> qualify in many respects as it has about the smallest useful instruction
> set going. It's biggest feature is the lack of complexity that allowed
> CPUs like the ARM and MIPS to be very fast as they were very simple
> compared to say the 386, the result was the amount of silicon required
> was less and production costs are lower. Some side effects of the smaller
> die(fewer transistors) were improved testability, lower power and less
> heat with attendant higher relibility. Most smaller RISC chips are 10s
> of thousands of transistors compared to millions in most of the CISC
> designs.

  Most people would consider the VAX to be the most CISCish of CPUs, but
with 16 general purpose registers and a very regular instruction format
(about the most regular format I've ever encountered, even including RISC) I
would almost consider the VAX to be RISCish in nature (although some
instructions like CRC might be a bit much 8-)

  I would give the Most CISCish Award to either the Intel 80286 or the Intel
432. The 80386 is byzantine, but they did (to an extent) regularize the
instruction set.

  -spc (Likes VAX assembly ... )
Received on Fri Jan 09 1998 - 01:06:51 GMT

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