bit addressing, alignment, bus errors, and VM (was Re: PDP-10 arch question)

From: Eric Smith <eric_at_brouhaha.com>
Date: Thu Oct 22 22:15:47 1998

Someone wrote:
> What machines have had bit pointers?

Allison replied:
> 8051. There may be others.

Bear in mind that on the 8051, bit operations could only be done on
certain specific bits of the internal register file. It didn't have true
bit pointers, so you couldn't do arithmetic on the pointers. And they
could only be used for single bits, not bit fields.

Aside from the PDP-10, the IBM Stretch (7030) and the TI 34010 and 34020
graphics processors had fully general bit addressing. The Stretch did
require floating point operands to be 64-bit aligned and instructions to
be 32-bit aligned. I don't think the 340xx had any data alignment
restrictions; I'm not sure about instruction alignment.

        http://www.brouhaha.com/~eric/retrocomputing/stretch/


Some unrelated stories about word alignement and virtual memory:


The 68K family generally required that instructions be aligned; before
the 68020 16-bit and 32-bit data was also required to be aligned. Otherwise
an address error exception occurred.

On the 68010 (but not the original 68000 (*)), it was possible to write an a
address error exception handler to take care of misaligned data.

On the 68020 and later, this could be done for instruction fetches as well.

Of course, the performance penalty was horrendous.


(*) The 68000 did not store enough of the machine state on the stack to allow
graceful recovery from bus errors and address errors. The 68010 dumps a
huge amount of data to the stack on these errors, 26 words (52 bytes), in
a 29 word stack frame affectionately referred to as the 'stack puke'. The
RTE instruction is thus able to restart the faulted instruction in midstream,
which is known as 'instruction continuation'. The 68040 and 68060, in
constrast, used an 'instruction restart' model. On a bus error or address
error, they undid any register alterations so that the instruction could
be restarted from the beginning when the exception handler returned. Of
course, RISC processors generally have simple enough instructions that the
instruction restart method can be easily implemented, possibly with the
need of some software assistance.

Actually on the 68000 if you carefully used an instruction for which the
behavior of the bus error on an operand access was well-known, it was possible
to recover from the bus error, provided you knew that no other unexpected bus
errors could occur. This technique of using a 'probe' instruction was used to
implement a crude form of virtual memory on the Lisa.
Received on Thu Oct 22 1998 - 22:15:47 BST

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