A vectored interrupt is one in which the interrupting device provides part
of the interrupt address. On the Z-80, this was done by the peripheral when
it saw the processor's interrupt acknowledge sequence and this meant that it
had to "see" both the M1 and the IORQ signals. It then reset its interrupt
logic when it saw the RETI instruction being fetched. As you may have
concluded, the Z-80 peripherals had to be as fast as the processor, and had
to have access to the necessary processor control signals.
I've never tried running a fast processor with slow peripherals and only
slow the processor down to the peripheral rate when M1 or IOREQ were active.
That might actually work so long as the peripheral had time to get its
bus-side task finished before its next transaction came along. That might
be a way to decouple the peripherals and processor. What I normally did is
run the I/O cycles slowly(4 MHz), insert a wait state in the M1 cycle, and
not use the Z-80 peripherals. That way I didn't have to present the M1 and
IOREQ signals to each peripheral.
Dick
-----Original Message-----
From: Arfon Gryffydd <arfonrg_at_texas.net>
To: Discussion re-collecting of classic computers
<classiccmp_at_u.washington.edu>
Date: Thursday, April 01, 1999 8:16 AM
Subject: Re: Computer busses.... (& Z-380)
>At 02:22 PM 4/1/99 +1, you wrote:
>>
>>> I'm thinking a stripped down Z-bus (without the M1 signal and etc).
What
>>> else should be on a bus besides:
>>
>>Maybe take a look at the Z380 Bus - again a design to include
>>the best ideas of two worlds (like the Z80 has been).
>
>I've got 4 Z380s!! I want to put together a parallel processor machine
>with a cool front panel of LEDs and switches.... I don't care for the
>Z380's extra pins like the Low address pin, medium address pin and hig
>address pins.
>
>Do I really need to connect the M1 pin to anything? I mean why would I need
>to insert wait states if the memory is faster than the processor?
>
>Explain something to me... On a reception of an INT signal, the processor
>jumps to a set memory location and starts executing the code. Right? What
>is a vectored interrupt (it's been a LONG time since I wired uPs and I
>can't remember.)?
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Received on Thu Apr 01 1999 - 09:31:05 BST