stepping machanism of Apple Disk ][ drive (was Re: Heatkit 51/4 floppies)

From: Allison J Parent <allisonp_at_world.std.com>
Date: Sun Apr 11 17:27:33 1999

<I have to disagree with your comparison of the 2 MHz 6502 with a 4 MHz
<Z-80A. My thought here is that the 4MHz Z-80 used in the conventional way
<had a memory cycle of 750 nanoseconds (3 clock ticks), while the 6502, at

No it did not. The memory active portion of the instruction cycle was
far shorter, typically 300ns at 4mhz (shorter for M1 cycle). the rest of
the time the cpu cares not if memory is there. Now if your depending on the
CPU for refresh it's longer but then again if you used something else it
still has to be done and takes some about of time/logic.

<had to go in order to utilize the memory bandwidth most effectively. The
<The 6502 could be interfaced quite easily by using an asymmetrical clock,
<with a short Phase-1 (the period during which addresses and control signal

The same can be done with the Z80 (the cmos parts it can be very effective).
I've used that trick to get a M1 read/ that has the same length as Mread/.

<In any case, what I determined was that the Z-80, in spite of its
<complicated hardware requirement, was potentially the faster processor.

I always get upset with this term as it's hard to quantitize unless standard
programs (sieve, fp-ops...)

Allison
Received on Sun Apr 11 1999 - 17:27:33 BST