<register assets, and simply look at what it takes to "do something" e.g.
<load a value, do some arithmetic, store a value, etc. the two instruction
<sets have considerable overlap. However, the longest instructions for the
<6502 take six (?) clock ticks, while the shortest ones for the Z-80 take
<four. (feel free to correct me, as I haven't even though about this, let
this is correct. Consider the timing as the z80 was using cycles in groups
of four (at 4mhz 1979). So a register moe or register to register add was
typically 1uS. Likely the 6502 at the time was 1uS as well. Don't count
clocks themselves the sysles were too different. Count the total time to
execute.
<know how long the longest instruction for the Z-80 takes nor do I even kno
21, LDIR (block move) and 23 (large group) of instructions that use
indexing through the IX and IY registers most of which have no analog
in 6502. for example SET b,(IX+D) (sets a bit at memory location.).
The last one takes 5.75uS at 4mhz. What counts now is what would it take
to do that using 6502.
<what its longest instruction is. I'd imagine it's one in which you load
<16-bit register from memory, indexed, or some such. That would have to tak
<a fair number of clock ticks.
load indexed is about 5uS. Lotas of clocks but they are used differently.
<In my comparisons, I've always fudged in favor of the Z-80, because it
<didn't make sense to me that a processor so cheap and simple would be as
<much faster than a Z-80 as the 6502 appeared. The hardware problems aside
the 6502 trades hardware complexity for some amount of speed and coves very
close but at about half the number of longer clocks.
<processor's instructions unless they are pushed. If you look at a simple
<load-the-accumulator then store-the-result, which occurs often in almost an
<application, the Z-80 takes about 6 ticks in the opcode fetch/decode (the
<instruction is decoded during the refresh cycle), three for each byte of th
<source address, then three to fetch the value. It then takes as long to
<store the result to memory. That's 6+3+3+3=15, twice is 30 ticks, or 7.5
<microseconds at 4MHz.
LDAX D ; load using DE as index
STAX B ; stor using BC as index
That is 7 clocks each or 14 total. _at_4mhz (1979) tht would be 3.5uS
the 6502 at 2mhz may do that in about the same time.
< The 6502 takes one to fetch the load opcode, one to
<fetch each byte of the source address, one to execute the load, one to fetc
<the store opcode, one for each byte of the destination address, and one to
<accomplish the store. That's 5 to load, 5 to store, which is 10, right? I
<would appear that the 6502 would get through this pretty quickly at the sam
<clock rate, i.e. 2.5 microseconds, but the problem is that external
<peripheral devices wouldn't run this fast. What's more, the 4 MHz parts,
<though priced a little higher than a 4 MHz Z-80, in 1980, the Z-80 had
<peripherals which would work very well together with the CPU at 4 MHz.
<Nevertheless, that's a 3:1 performance ratio which, based on the fact that
<there were many more register-to-register (quick) operations available to
<the Z-80 programmer, it's hard to imagine these would close the gap that
<much. They would have a significant impact, though.
It does depending on the application. If a lot of 16bit adds and subtracts
were part of the "core" then were is the 6502? How about languages that
use really deep stacks?
what about really deep recusive code? The z80 has a far larger stack
limit! Granted 128 calls is a lot but none of that stack can pass
parameters either, so you need to use one of the index register for that.
Also there is interrupt structure for multiple complex devices. Z80 allows
a 7 bit vector (pointer to table, anywhere in ram) for mode 2. Even mode0
(8080) it has 8 vectors in low memory (one is reset). using the Mode 1
you still have two (NMI and INT/).
Hardware wise can the 6502 support DMA, the z80 has busreq/ and busack/
to request the bus from the cpu and get acknowledgement that it has.
How much ram space does the 6502 have to give up for a typical spread of
devices verses seperate IO space (z80). Keep in mind if memory mapped IO
is desired the z80 does that too.
<I think you can easily build a circuit with a 2 MHz 6502 and one with a 4
<MHz Z-80 and make a comparison yourself. If you honestly try to take
<advantage of the instruction set to accomplish a task on both processors,
<you'll play HELL getting the Z-80 to keep up. It can be done, though, if
Depending on the mix it would favor one or another but when averaged out
the z80 wins or at best matched. There are other factors that may be
system implementation dependent that may favor one over the other.
<the task is chosen properly. A pair of simulators would be really handy,
<wouldn't it?
there are tons for the z80 but few if any do cycle counts or other timing.
They could be done for the 6502 but... their performance would have to be
validated against the real parts to insure the simulations arent biased.
Allison
Received on Sun Apr 11 1999 - 17:28:21 BST