This is gates, not macrocells. I imagine it could be done with just a CPLD,
like one of the mid-sized ~384 macrocells including the steering logic and
instruction sequencer. It only needs eight 8-bit registers including the
impending operand register.
-----Original Message-----
From: Allison J Parent <allisonp_at_world.std.com>
To: Discussion re-collecting of classic computers
<classiccmp_at_u.washington.edu>
Date: Sunday, April 11, 1999 9:46 PM
Subject: Re: stepping machanism of Apple Disk ][ drive (was Re: Heatkit 51/4
floppies)
><You can build your own in an FPGA for something on the order of 2500 gates
>
>Gates or CPLDs? Big difference there. I do ahve a few 3030s here and can
>get 4000 seris. But why would I do it.
This would depend on the available resources. The Xylinx parts tend to come
up short on routing resources. Last time (hopefully) I worked with the old
3000-series parts we were always having to cut and jumper our boards because
the routing resources weren't there to preserve our pinout. I also found
the 3000 series doesn't integrate well. It's best if you can partition a
function to fit the FPGA. Sharing logic cells uses too many pins. It's
easier and perhaps more efficient to replicate some functions versus sharing
them from either the internals of one LCA or from a common external source.
>then again I have an early 80s project that was a z80 built in 2901s...
>at a time where a 10mhz z80 was an extreme machine.
>
>Allison
>
Received on Sun Apr 11 1999 - 22:58:47 BST