z80 timing... 6502 timing

From: Allison J Parent <allisonp_at_world.std.com>
Date: Mon Apr 12 21:17:01 1999

from my ampro LB using calibrated logic analyser...

 Tc = 1/clock z80A 4mhz or 250ns (clock is symetric)

address stable before Memreq/ ~80nS (occurs 0.5clocks earlier
                                              than read or wr -delays)
 WR/ width 210ns (roughly 1 clock -delays)
 RD/ width (M1) 290us (roughly 1.5 clocks -delays
 RD/ width (other) 390us (roughly two clocks -delays)

So the longest memory use cycle is address setup+ RD/ or about 470us.
Even the rom chip select was active for less than 400ns and that includes
propagation delays. the 4mhz z80 wants memories with access times in the
250ns range.

In terms of memory bandwidth used the z80 runs from a high of 80% on M1
cycles (due to z80 providing memory refersh) to around less than 50% on
other read or write cycles. Refresh is not a required signal for operation
with static rams so the M1 memeory bandwidh can be less than 50%. This
set of statements is also inaccurate as it is worst case for some
instuctions. In those cases like ADD DE,HL that takes many cycles but the
only bus useage is during M1 so the average bandwidth can be very low.

To get 750ns I need to slow the clock to about less than 2mhz or add the
time for m1 and refresh at 4mhz. In either case it's apples and oranges.

The 6502 _at_2mhz would want 300ns memory. An aside to this is that the
6502 like many cpus use both edges of the clock to trigger functions via
a two phase internal clock so there are roughly 4 phase pulses per cycle
internally. the external timing of the 6502 looks simpler due to it's
use of signals and the synchronous nature of the machine. this is wny
external clock frequency is so meaningless. Instruction execution time
is the only measure.

the 6502 memory useage is far higher as it is active for half the
processor cycle so it's roughly 50% in all cases. This makes hidden
refresh of Drams easier with the regular cycle timing but allows less
time to achieve it. If the refresh is done during the inactive portion
of the 6502 cycle then memory bandwidth nears 100% use. The exception
is if the memory is fast enough it can be done with post read refresh
(cas after ras). Static rams will run at ~50% of bus bandwidth.

Allison
Received on Mon Apr 12 1999 - 21:17:01 BST