Well, Allison, I now see why this discussion has led nowhere. We were
addressing the same issue from different perspective. You were looking at
the relatively short memory access strobe, while I was talking about the
frequency at which they occur, as defined in the spec. I agree completely
that the memory read access strobe, something on the order of /mreq + /rd
(which should yield a more or less appropriate /memrd) is quite short and
that the write strobe is probably a bit shorter. What I was doing by tying
these strobes to the processor clock period (ticks, cycles, whatever you
like) was finding a way in which the overall rate at which they occur could
be discussed without getting into the gate-level strategy of building the
strobes themselves. That is, after all, a matter of style, and quite
personal. The fact remains, that the memory CYCLE is three clock ticks
long, as defined in the spec (though I haven't looked at it in 15 years or
so since I haven't yet unearthed my Zilog or Mostek data books) and if you
look at the pictures you saw with your logic analyzer, you should have seen
two read pulses of whatever lenght they were, spaced at very nearly 750 ns,
each time you saw the execution of an absolute jump, or any other
instruction which consists of an opcode followed by a 16-bit address. The
same is true of writes. They take one memory cycle, which is three clock
ticks long, for each byte, although the memory write strobe is a mite
shorter than the read strobe, IIRC, which I might not, but . . .
What it comes down to is that the non-M1 memory cycles of a typical 2 MHz
6502 take one clock tick, or 500 ns, while the actual memory read strobe can
be as short as you like within the window during which valid addresses are
available and ending when the Phase-2 clock falls. As you've pointed out,
the M1 processor cycle, comprised of the opcode fetch (a shortened memory
read) and the refresh cycle, (during which the instruction was decoded and
the memory refresh strobe asserted concurrently with the 7-bit refresh
counter), was a bit longer, one or two clock ticks, and more if wait states
were inserted as they often were for M1 cycles. Nevertheless, commonly used
instructions were MUCH faster on the 2 MHz 6502, than on the 4 MHz Z-80.
Offsetting this, however, the Z-80 had lots of instructions which operated
on internal registers, leaving memory idle. If you executed a direct jump,
which on either processor meant "load the program counter with the following
two bytes," The Z-80 required at least five, and perhaps six clock ticks to
get to the first address fetch, which took, overall three clock ticks,
followed by another three for the second byte. This would amount to 12
clock ticks if my reckoning is correct for the AMPRO Little Board, of which
I also have a couple, and on that board, running a 4 MHz Z-80A, you will
probably measure three microseconds for those twelve clock ticks (T-states)
which is EXACTLY how long a 1 MHz 6502 takes to do that. Hence, I conclude
it is just about twice as fast for that type of instruction on a 2 MHz 6502.
How long the memory strobes are doesn't affect the duration of the cycles at
all. After looking a what seems like about a billion lines of code over
the years since I saw my first one back in the very early '60's (CDC-6400)
I've concluded that most code I've seen underutilizes the internal resources
and overutilizes the external ones. Code like that favors processors with
more time-efficient use of the external resources. Hence, my assertion that
there's reason to believe the 6502 at 2 MHz could outrun the 4 MHz Z-80 in
more or less typical code and in a more or less typical hardware
environment. Code written to make better than average utilization of the
internals of a Z-80 might fare better against equally well-written code on a
6502. I'm comfortable with the reality that I'll probably never know for
certain. Since neither processor is particularly important these days, not
terribly important to me either.
None of this is really worth getting all excited about because, by the way,
in spite of its "better" performance, (by my assessment) the 6502 didn't
accomplish more useful work on MY behalf, because I used a Z-80 running CP/M
every chance I got due to the abundance of really decent tools and office
automation software.
Dick
-----Original Message-----
From: Allison J Parent <allisonp_at_world.std.com>
To: Discussion re-collecting of classic computers
<classiccmp_at_u.washington.edu>
Date: Monday, April 12, 1999 8:24 PM
Subject: z80 timing... 6502 timing
>from my ampro LB using calibrated logic analyser...
>
> Tc = 1/clock z80A 4mhz or 250ns (clock is symetric)
>
>address stable before Memreq/ ~80nS (occurs 0.5clocks earlier
> than read or wr -delays)
> WR/ width 210ns (roughly 1 clock -delays)
> RD/ width (M1) 290us (roughly 1.5 clocks -delays
> RD/ width (other) 390us (roughly two clocks -delays)
>
>So the longest memory use cycle is address setup+ RD/ or about 470us.
>Even the rom chip select was active for less than 400ns and that includes
>propagation delays. the 4mhz z80 wants memories with access times in the
>250ns range.
>
>In terms of memory bandwidth used the z80 runs from a high of 80% on M1
>cycles (due to z80 providing memory refersh) to around less than 50% on
>other read or write cycles. Refresh is not a required signal for operation
>with static rams so the M1 memeory bandwidh can be less than 50%. This
>set of statements is also inaccurate as it is worst case for some
>instuctions. In those cases like ADD DE,HL that takes many cycles but the
>only bus useage is during M1 so the average bandwidth can be very low.
>
>To get 750ns I need to slow the clock to about less than 2mhz or add the
>time for m1 and refresh at 4mhz. In either case it's apples and oranges.
>
>The 6502 _at_2mhz would want 300ns memory. An aside to this is that the
>6502 like many cpus use both edges of the clock to trigger functions via
>a two phase internal clock so there are roughly 4 phase pulses per cycle
>internally. the external timing of the 6502 looks simpler due to it's
>use of signals and the synchronous nature of the machine. this is wny
>external clock frequency is so meaningless. Instruction execution time
>is the only measure.
>
>the 6502 memory useage is far higher as it is active for half the
>processor cycle so it's roughly 50% in all cases. This makes hidden
>refresh of Drams easier with the regular cycle timing but allows less
>time to achieve it. If the refresh is done during the inactive portion
>of the 6502 cycle then memory bandwidth nears 100% use. The exception
>is if the memory is fast enough it can be done with post read refresh
>(cas after ras). Static rams will run at ~50% of bus bandwidth.
>
>Allison
>
Received on Mon Apr 12 1999 - 23:27:35 BST