The rule of thumb back in the '70's was that TTL was "good" to 25 MHz.
Current generation FPGA's routinely operate at 10x that speed, while, in
reality, it was an exceptional TTL design of the '70's that would allow a
significant bit of circuitry, e.g. a FIFO or a synchronous state machine, to
operate across more than a very few bits at that speed. Typical prop-delays
of 10-15 ns would add up quickly. (remember that we've since then learned
about pipleine registers, which were not in common usage then.)
The latest (e.g. VIRTEX) families boast synchronous performances of 500 MHz
for such structures, though their CLB's (configurable logic blocks) have
prop-delays of under a ns and clock-to-q prop's in that range as well.
Those CLB's are really lookup tables in which you program a random function
of up to 5 variables, hence get the same prop whether it's a nand or an
xnor.
It would take a clever designer indeed to get anywhere near the top level of
performance with a rework of the PDP-11 processor, but it's been attempted.
There are more than one of them out there, though I haven't kept up on that.
Nevertheless, if you do it, particularly in a popular HDL, you're developing
essentially your own intellectual property, and in a portable medium which
you can use with any vendor's product.
Dick
-----Original Message-----
From: allisonp_at_world.std.com <allisonp_at_world.std.com>
To: Discussion re-collecting of classic computers
<classiccmp_at_u.washington.edu>
Date: Friday, August 27, 1999 6:35 AM
Subject: Re: PDP era and a question
>> The technology in FPGA's these days is such that it enables devices to
>> operate between 10 and 50 times the speed of the old TTL logic designed
in
>
>Old ttl was nowhere near that much slower. The lowly 7400 in 72 was
>comfortablly under 15ns, true the FPA part may be under 1ns now but...
>that's not 50X! Of course adding interconnection delays and other factors
>the 10x number is very honest.
>
>> the '70's. That doesn't mean you can take a '70's design and
>> "transliterate" it and make it run lots faster, though that is
conceivable.
>
>This is true of any from one logic system to another. PDP-8 for example
>used a lot of "wired or" and similar logic in the data paths to conserve
>gates. Of course that was a slower way to do it but lower cost too.
>So a design translation can buy speed at the cost of logic or design
>effort.
>
>> Schematic entry would be the easiest way to clone the prints, but HDL is
>> considered by many to be the best way to implement an architecture, the
>> behavior of which is well defined and understood. If you build your
device
>> in VHDL or VERILOG, it is inherently portable, since both XILINX and
Altera,
>> among others, support both.
>
>VHDL is the way to go but developing the description would be the real
>work.
>
>> access to the resources to implement it in a product they sell, provided
you
>> buy the parts from them. They cost a few dollars in small quantity, but
if
>> you say the right "things" when approaching them, and seem sufficiently
>> eccentric, they'll treat you right.
>
>Roger that. Besides, they know if you do one your likely to use it for
>other things (drag factor).
>
>Allison
>
Received on Fri Aug 27 1999 - 10:20:53 BST