> > > WP... workspace pointer. back when the 9900 was new registers (memory)
> > > really ate up chip space and TI had an archetecture in the 990 minicomputer
> > > where register were in memory instead of in the CPU. So the WP is a pointer
> > > that points to a block of 16 locations in ram that are addressed in
> > > instructions as R0 through R15.
> > Wow! What a cool architecture! That would be a very handy feature to
> > have in any processor.
> The disadvantage is that the registers are in main memory, so accessing
> them is slower than accessing them if they were on the CPU.
Nop, or better depending on the structure of your processor.
for example, take one the most costly (basic) operation:
Copy one register into another
cycle 0 read operation,
cycle 1 decode,
cycle 2 read word
cycle 3 write word
Address calculation hidden while cycle 1 and 2.
On first sight we could save cycle 3, to need only
read/decode/move, but when you have your 16 Registers
on chip, you need a 16 by 16 multiplex just for this
one instruction (and thats a whole lot of silicon
back then - not to mention additional decode logic
to detect when source and destination is the same.
While when using an ALU structure CPU, like common
back these days, you need still 2 cycles read&feed
ALU and store result. So if the CPU has no interleaved
execution (needs again more silicon) you end up with
same amount of cycles needed - just less bus load, but
who cares bus load ?
Remember, around 1980 Mem was still faster or at least
as fast as CPUs. 200ns RAM could well perform in an
4 MHz system - and a 4 MHz CPU was quite a fast babe.
So the design just added an ernormous amout of fexibility
without drawbacks. Remember, the 9900 was also ment to be
a simple mid to low range CPU.
> A few other CPUs have tried something similar. The 6809 has a 'direct
> page', which is like the 6502's zero page, except that it can be any
> 256-location page in memory. The top byte of the address of this page
> comes from a register in the processor. So on a context swtich, all you
> have to do is change this register and save the CPU accumulators, index
> registers, etc.
Kind of. The 6502s Zeropage is more like an extended register set
of 256 8 Bit or 128 16 Bit registers, without any proposed structure.
And you are still fixed within a TBD structure, while the 9900 just
changed all registers to a new value just by changing the WP.
The 9900 is comperable to several Register Window designs of
RISC processors. Nowadays, where the CPU runns art higher speed
than MEM, _and_ several 1000 gates more for every instruction to
save a cycle is seen as a bargain the huge silicon toll is no
burdon.
> The PERQ 1a and later have a very interesting feature. A register index
> register (!). These machines have 256 processor registers on the CPU
> card. A microinstruction selects which registers to use by a couple of
> 8-bit fields in the microcode word. But on the 1a and later, there's an
> 8-bit register on the CPU card that's ORed with the register address from
> these microcode fields if the instruction references one of the first 64
> registers. Normally the index register is left set to 0, so it has no
> effect, but I believe it has been used for context switching (to say move
> a block of 16 'user' registers around in the CPU register space).
> Equally you can select any register by loading its address into the index
> register and referencing register 0.
Nice implementation - low hardwarecount (from todays sight)
but realy flexible, since it could do more than just store
several register sets, but rather give 256 registers accessable
at all times (a bit like 6502 zero page).
Gruss
H.
P.S.: I've been told there was a Nixdorf computer where they
build a (TTL) CPU based on the 9900 design.
--
Ich denke, also bin ich, also gut
HRK
Received on Mon Feb 01 1999 - 11:17:38 GMT