Fw: Pre-history of Digital Research

From: Allison J Parent <allisonp_at_world.std.com>
Date: Sat Mar 20 16:55:49 1999

<designs of yesteryear. Back then we were still learning about race
<conditions and setup and hold time violations, and the like. Back then, a
<circuit designed to operate from a 25 MHz clock was taxing the limits of th
<technology, while today, people don't even blink when the clocks are over 1
<times that fast.

While the parts werent fast and there were things to be aware of it wasn't
that backward. There were however sloppy designers doing sloppy designs.

I did a PLL design, direct counting to 50mhz in 1973, that was near the
TTL upper limit but not that hard to do. Doing 25mhz plus logic in 1975
was not unheard of and Mini makers were doing it but there were economic
issues in doing that not technical.

The most common errors were lousy board layouts and weak ground planes.
the altair suffered from both severly. Another fault was many designers
were forgetting that backplanes and other busses were trnasmisstion lines
and needed to be terminated properly, again the altair was the worst going
from the front pannel to the bus with a bundle of wires the shortest near
6 inches long. Even at 2MHz this was sloppy practice. Looking at
contemporary DEC and DG backplanes for the time it was clear the design
techniques were known.

Don't forget in 1989 (-10y) a PC running at 25mhz was the hottest thing
going. It would take another decade to get from 25 to 250+ as a mator of
routine for PCs but there were system going much faster than PCs in 1989.


Allison
Received on Sat Mar 20 1999 - 16:55:49 GMT