Fw: Pre-history of Digital Research

From: Richard Erlacher <edick_at_idcomm.com>
Date: Sat Mar 20 18:11:52 1999

There were PLL devices I played with back then, e.g. Signetics 564, among
others, which boasted 50 MHz operation, but standard TTL logic was spec'd at
20-25 MHz at the top end, frequency wise, and one had to use H-TTL or S-TTL
to make your circuitry remain within specified limits. If you weren't into
worst-case analysis, you might get away with operating a circuit outside
those limits more often than not, but while the cases that worked might on
occasion get you some praise or a bonus, the ones that didn't would
absolutely get you fired. Back in those days, although the S-TTL ran some
50-75% faster, it cost well over double, if the function you needed was
available. It often required that several parts be replaced with schottky
parts to avoid races, as synchronous design was not yet as popular as it is
today, and synchronous circuitry has to have everybody synchronized with the
same clock, hence, able to function at the schottky rate which increased the
cost even more.

I'll stick with my earlier complaint, that the most annoying problems I saw
back then were unconnected inputs and races, both of which became VERY
troublesome when a substitution of either LS or, worse, HCMOS parts was made
as the product matured. Often this required extensive redesign, frequently
with the addition of pipeline registers to synchronize asynchronous events,
which made for ugly reworks.


-----Original Message-----
From: Allison J Parent <allisonp_at_world.std.com>
To: Discussion re-collecting of classic computers
Date: Saturday, March 20, 1999 4:02 PM
Subject: Re: Fw: Pre-history of Digital Research

><designs of yesteryear. Back then we were still learning about race
><conditions and setup and hold time violations, and the like. Back then, a
><circuit designed to operate from a 25 MHz clock was taxing the limits of
><technology, while today, people don't even blink when the clocks are over
><times that fast.
>While the parts werent fast and there were things to be aware of it wasn't
>that backward. There were however sloppy designers doing sloppy designs.
>I did a PLL design, direct counting to 50mhz in 1973, that was near the
>TTL upper limit but not that hard to do. Doing 25mhz plus logic in 1975
>was not unheard of and Mini makers were doing it but there were economic
>issues in doing that not technical.
>The most common errors were lousy board layouts and weak ground planes.
>the altair suffered from both severely. Another fault was many designers
>were forgetting that backplanes and other busses were trnasmisstion lines
>and needed to be terminated properly, again the altair was the worst going
>from the front pannel to the bus with a bundle of wires the shortest near
>6 inches long. Even at 2MHz this was sloppy practice. Looking at
>contemporary DEC and DG backplanes for the time it was clear the design
>techniques were known.
>Don't forget in 1989 (-10y) a PC running at 25mhz was the hottest thing
>going. It would take another decade to get from 25 to 250+ as a mator of
>routine for PCs but there were system going much faster than PCs in 1989.
Received on Sat Mar 20 1999 - 18:11:52 GMT

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