Computer busses....

From: Arfon Gryffydd <arfonrg_at_texas.net>
Date: Tue Mar 30 12:48:34 1999

>You've hit most of the important signals. One I'd add, however, is a data
>bus disable, and perhaps an address bus disable as well. This would allow a
>front panel or other bus mastering device to steal cycles under certain
>circumstances.

Why wouldn't BUS REQUEST work?



>What would you do with the HALT signal, and how would you implement it?

WAIT sould act as a "pause and hold the bus in it's current condition"
signal. Halt should mean "Stop what you are doing, release the control of
the bus and wait until the HALT signal is removed". IMHO



>There's some debate about how one should signal the beginning of a new bus
>cycle. This should be at the earliest moment at which addresses are
>stable.

I guess the RD/WR signals should be seperate and only applied AFTER all
signals on the bus are stable.


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Received on Tue Mar 30 1999 - 12:48:34 BST

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