Rebirth of IMSAI

From: Allison J Parent <>
Date: Tue Mar 30 17:59:41 1999

<It was always somewhat of a nuissance dealing with the Z-80 because of the
<way it presented its interrupt acknowledge, which was a combined I/O and M
<cycle, as long as the I/O cycle, but with M1. That meant, in my case, tha

All instuction fetch cycles were short, INTA cycle had an extry cycle added
for interrupt resolution in the supporting chips.

To get around the short M1 cucles I'd use a tiny bit of logit to stutter
the clock to the chip (slip a cycle) for M1 only. This results it running
generally faster and still using slower memory.

<This same protocol made it unwise to try to use memory mapped I/O, since th
<cycle length of an I/O cycle differed from that of a memory cycle.

I used to do it all the time and like I posted earlier the NS* disk system
used MM-IO very effectively.

Received on Tue Mar 30 1999 - 17:59:41 BST

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