While I appreciate all the suggestions I've been getting, what I'm after is
an answer to the question I've put forth. The 8-bit interface feature is
written in the purported ANSI standard for ATA interfacing, yet nobody seems
to have experience with it. I was hopeful that someone would know about
this.
No, I'm not interested in the older "pre-standard" 8-bit standard which was
referred to in the proposed v.1 standard in the following remark from the
standards committee meeting notes prior to the release of the initial
standard.
"I recommend that Section 6.2.5 be replaced with the following:
The data register is either 8-bits or 16-bits depending on the
interface width currently selected and/or the type of data
being transferred by the current command. This register is
used only by PIO data transfer commands."
it goes on in reference to another feature-related command . . .
"8.22. SEEK
TYPE - Manadatory.
PROTOCOL - Non-data.
INPUTS - The Cylinder High, Cylinder Low, head portion of the
Device/Head register and the Sector Number register contain the
logical sector number in CHS or LBA mode to which the device
should move the read/write heads.
OUTPUTS - Same as the input registers.
PREREQUISITES - None.
DESCRIPTION - This command initiates a seek operation to the
physical cylinder and head that contains the target logcial
sector. If the device supports the indication of seek in
progress and seek complete by clearing and setting the DSC bit in
the Status register, then the device shall set DSC=0 when the
seek operation is started and shall not set DSC=1 until the seek
operation has completed. The device may clear BSY and generate
an interrupt before the seek is completed.
Devices that implement power management may not perform the seek
operation if the current power state is Idle or Standby.
If another command is issued to the device while BSY=0 but DSC=1,
the device sets BSY=1, waits for the seek to complete, and then
begins execution of the command.
ERRORS - ID Not Found and Command Abort.
8.23. SET FEATURES
TYPE - Optional.
#############################################################
#
#Hale's note: Oh, come on now, we all know that Set Features
#really isn't optional any more!
#
#############################################################
PROTOCOL - Non-data.
INPUTS - The Feature register contains a subcommand code as
described in table 14. Some subcommands use other registers,
such as the Sector Count register to pass additional information
to the device.
OUTPUTS - See the subcommand descriptions.
PREREQUISITES - None.
DESCRIPTION - This command is used by the host to establish the
following parameters which affect the execution of certain device
features as shown in table 14.
+=====+=============================================================+
| 01h | Enable 8-bit data transfers (see 6.2.5) |
| 02h | Enable write cache * |
| 03h | Set transfer mode based on value in Sector Count register |
| 33h | Disable retry * |
| 44h | Length of vendor specific bytes on READ LONG/WRITE LONG cmds|
| 54h | Set cache segments to Sector Count register value * |
| 55h | Disable read look-ahead feature |
| 66h | Disable reverting to power on defaults (see 8.23) |
| 77h | Disable ECC * |
| 81h | Disable 8-bit data transfers (see 6.2.5) |
| 82h | Disable write cache * |
| 88h | Enable ECC * |
| 99h | Enable retries * |
| AAh | Enable read look-ahead feature |
| ABh | Set maximum prefetch using Sector Count register value * |
| BBh | 4 bytes of vendor specific byts on READ LONG/WRITE LONG cmds|
| CCh | Enable reverting to power on defaults (see 8.23) |
|-----+-------------------------------------------------------------|
| | *These feature definitions are vendor specific |
+=====+=============================================================+
Table 14 - Set Features register Definitions
All values not contained in Table 14 are reserved for future
definition.
At power on, or after a hardware reset, the default mode is the
same as that represented by values greater than 80h. A setting
of 66h allows settings of greater than 80h which may have been
modified since power on to remain at the same setting after a
software reset.
A host can choose the transfer mechanism by Set Transfer Mode and
specifying a value in the Sector Count register. The upper 5
bits define the type of transfer and the low order 3 bits encode
the mode value.
PIO Default Transfer Mode 00000 000
PIO Default Transfer Mode, Disable IORDY 00000 001
PIO Flow Control Transfer Mode x 00001 nnn
Single Word DMA Mode x 00010 nnn
Multiword DMA Mode x 00100 nnn
Reserved 01000 nnn
where "nnn" is a valid mode number for the associated transfer
type.
(Editor's note: It is intended that the reserved values be used
for future specification of an alternative flow control
mechanism.)
If a device supports this specification, and receives a SET
FEATURES command with a Set Transfer Mode parameter and a Sector
Count register value of "00000 000", it shall set its default PIO
transfer mode. If the value is "00000 001" and the device
supports disabling of IORDY, then the device shall set its
default PIO transfer mode and disable IORDY.
See vendor specification for the default mode of the commands
which are vendor specific.
Devices reporting support for Multi Word DMA Transfer Mode 1 must
also support Multi Word DMA Transfer Mode 0.
Support of IORDY is mandatory when PIO Mode 3 is the current mode
of operation.
ERRORS - If the device does not support the command or if any
input value is is not supported or is invalid, the device posts
an Aborted Command error."
and is referred to in the meeting notes prior to release of the 1996
standard in the context of being discontinued.
In the 1994 standard, which is the main one I've been studying, the 8-bit
mode is handled as just another feature.
Clearly this is a standard feature, but I'm not comfortable that it was
actually implemented as a standard.
Any light that could be shed on this matter in specific terms, would be
helpful.
Dick
----- Original Message -----
From: Hans Franke <Hans.Franke_at_mch20.sbs.de>
To: <classiccmp_at_classiccmp.org>
Sent: Monday, April 17, 2000 7:24 AM
Subject: Re: 8-bit IDE
> > > Recently, as part of my effort on an S-100 "hard-card" using a 2-1/2
> > > inch ide drive, I've been revisiting the 1994 standard for the ATA
> > > interface. There's a not-too-detailed mention of an 8-bit mode which
is
> > > set up using a bit in register. This feature was apparently obsoleted
> > > as of 1996's standard.
>
> > It's actually not that hard to use a normal 16 bit IDE drive in an 8 bit
> > system (like an S100 card). You need a few buffers/latches to convert
> > between 8 and 16 bits on read/write, that's about it.
>
> > Actually, although it pains me to say this, IDE drives are so cheap per
> > megabyte now that you could probably get away with wasting every other
> > byte... Just use a 3-state buffer to always write the top 8 data lines
as
> > 0 (or FF or...) and ignore them on read. After all, people give away 1Gb
> > IDE drives these days (or so I've heard), and 500M of storage (i.e.
> > wasting every other byte) is massive for S100 systems.
>
> Quite an inriguing idea. You also will get 256 Byte records ...
> a more common size back then. Well, what about commands etc. pp ?
>
> Gruss
> H.
>
> --
> VCF Europa am 29./30. April 2000 in Muenchen
> http://www.vintage.org/vcfe
> http://www.homecomputer.de/vcfe
Received on Mon Apr 17 2000 - 09:39:37 BST