8-bit IDE

From: Richard Erlacher <edick_at_idcomm.com>
Date: Tue Apr 18 10:13:01 2000

please see embedded comments below.


----- Original Message -----
From: <allisonp_at_world.std.com>
To: <classiccmp_at_classiccmp.org>
Sent: Tuesday, April 18, 2000 7:33 AM
Subject: Re: 8-bit IDE

> On Mon, 17 Apr 2000, Richard Erlacher wrote:
> > My experience with Q-Bus I/O was always spoon-fed via a DRV11-WA card.
> Qbus output address at Bsync/ (like 8085 ALE) and you latch the address
> off the databus, plus BBS7 (bankselect 7 is the IOpage) and theres your
> address. The next part of the cycle is typically an IO_read with an
> optional IO_write to follow. What makes doing IDE on PDP11 is the read
> before write to the same address (plays havoc with device resgisters).
> the simple solution is to map all reads to base+0 to base+n and writes
> to base+N to Base+n+n so reads do not overlap writes.
So you'd advocate essentially using the Write signal (forgive me if I don't
remember which name that one wore) as an address line, kind of like the
AMPRO folks did on their FDC?
> Allison
Received on Tue Apr 18 2000 - 10:13:01 BST

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