8-bit IDE

From: Richard Erlacher <edick_at_idcomm.com>
Date: Wed Apr 19 00:09:31 2000

Please see my comments below.

Dick
----- Original Message -----
From: John Wilson <wilson_at_dbit.dbit.com>
To: <classiccmp_at_classiccmp.org>
Sent: Tuesday, April 18, 2000 6:29 PM
Subject: Re: 8-bit IDE


> On Tue, Apr 18, 2000 at 06:11:15PM -0400, allisonp wrote:
> > Limited logic, one latch. No rule said only one address for the data
read
> > or write.
>
> I'm curious, how can it be done with just one latch? In my ISA-8 thing,
> I used one latch for writing data, to hold the low byte until the PC
writes
> the high byte. And another in the other direction, to catch the high byte
> when the PC reads the low byte. Then a 244 to allow writing the high
byte,
> and a 245 for all other cases (including 8-bit register accesses). Is
there
> some way I'm not thinking of, to flip one 373 around and use it in both
> directions???
>
keep the 'LS646 in mind. It contains the equivalent of a pair of '574's
with a '245 wired across the two registers. You can transfer data in
pipelined mode or in immediate mode, which potentially would allow you to
reverse byte order, for example, by passing the first received byte to the
register and the second to the outputs. This works in either direction.

Allison mentioned a strategy that would enable you to do this with a single,
albeit bidirectional register (e.g. LS646). If you decode the data bus high
byte and low byte separately, you could write to the lower byte at one
location and write to the higher at another, which, coincidentally, turns on
the outputs of the lower register, while presenting the output from the bus
receiver on the high byte. Likewise, if you read from the high byte
directly, using the enable to the high byte as the latch strobe to the
registered low-byte, you can later read the low byte. This, unfortunately
reverses the byte order.

OTOH, if you write the low byte and register it in a '646, and then write
the high byte into another '646, you need to wait until the write cycle is
ended, since that is guaranteed only on the trailing edge of the write
strobe pWR* since the '646 is rising-edge sensitive. If one were to use a
'573, one could write the low byte with no transaction on the IDE channel,
followed by a write of the high byte, during which the low byte output is
enabled, thereby effecting a word write. The register in the high-byte's
'646 would only be used in the case of a read from the IDE. The physical
IDE 16-bit channel would be latched on the high byte with its output enable
turned off, while the low byte is read through the transparent latch.
Unfortunately, these devices are edge-triggered rather than level gated
registers. That requires a separate read cycle that occurs only AFTER the
IDE is registered.

> John Wilson
> D Bit
Received on Wed Apr 19 2000 - 00:09:31 BST