>>2. The Catweasel uses a proprietary, largely undocumented programming
>>interface. My circuitry is entirely open, and I think it's pretty easy
>>to program. (My first hack at acquiring data with the new buffer was
>>dashed off in about half an hour under QBASIC.)
>Thier doc's pretty much stink, or at least did when I got mine!
It sounds like John Wilson has reverse-engineered at least *some* of
their programming interface, though last I heard there were parts of
the interface that were a mystery even to him :-).
>>Would it be worth writing up my new floppy disk data buffer so that
>>others could improve on it? Would anyone be interested in unstuffed and/or
>>stuffed PCB's? Should I give it a name? (The "Timweasel", anyone? I
>>gotta think of a better name!)
>Maybe/probably.
It looks like my circuit can be put on roughly a 3" x 4" PCB, meaning
that after paying for ExpressPCB overhead it'll be maybe $20 or so per
PCB in small quantities. The PCB would have a 24-pin header for interfacing
to a PC-clone parallel port (or whatever cabling you want to any other sort
of parallel type port on another hardware platform), and 34-pin and 50-pin
headers to hook to 3.5", 5.25", and 8" disk drives. I haven't priced
the chip costs, but they'll probably total around $25 or so from a hobby
place like Jameco or from a real distributor like Digi-Key.
Chip lineup in my current design:
1 62C1024 128K*8 SRAM.
1 74HCT373 for latching control signals from parallel port, 3 of
the outputs are used to drive the head load and step/direction
lines to the floppy drive.
8 MHz crystal clock.
1 74HCT74 for bi-phase clock generation and pulse synchronization from
the floppy read line
2 74HCT175's to make a seven-stage ring counter. Only 3 phase outputs are
used, one to latch and increment the counters, one to latch the
outputs of the shift register, and one to do the write enable.
1 74HCT164 for taking serial data from the 74HCT74 pulse synchronizer
and turning it into 7-bit wide parallel out.
(The 8th bit comes from the index line).
1 74HCT374 for latching the shift register data and tri-stating it onto
the memory buffer bus.
1 74HCT04 and 1 74HCT00 for gating and inverting as necessary
2 74HCT590's and 1 74HCT93 for making a 20-bit buffer address counter.
(17 bits are used in the current implementation, though
we obviously could just drop in a bigger SRAM and use
the extra address bits.)
I took some pains in my design to allow things to be sped up for more
oversampling at a later date. (I'd probably want to replace the 74HCT93
with a third 74HCT590 just to make all the address counters fully
synchronous, but I only had 2 HCT590's in my junk box when I built this
implementation). The timing from the ring counter and the
rest of the HCT logic ought to make sampling up to 40 MHz very straightforward
(I'd have to lengthen the write-enable from the ring counter at higher
clock speeds to cover a couple of clock phases).
> It would be nice to stuff one in a Linux box, or will it
>work in an Alpha under VMS :^)
Anything with a bidirectional parallel port oughta work fine.
--
Tim Shoppa Email: shoppa_at_trailing-edge.com
Trailing Edge Technology WWW: http://www.trailing-edge.com/
7328 Bradley Blvd Voice: 301-767-5917
Bethesda, MD, USA 20817 Fax: 301-767-5927
Received on Tue Jul 04 2000 - 13:06:52 BST