Tim's own version of the Catweasel/Compaticard/whatever

From: Richard Erlacher <richard_at_idcomm.com>
Date: Tue Jul 4 14:51:07 2000

The only problem I'd point out is the the 9500 series CPLD's drive only 8 mA
per output and, unless you were planning to pair them up, i.e. use multiple
pins tied together to drive the FD cable, you might have problems.

I don't know about Tim's design, but I'd say the necessary logic to
interface via EPP will easily fit in the XC9572, and, in fact, one might
find an easy enough way to make an FDC fit in there as well.

The parts count with a SCENIX SX would be be lower, though, in that you need
one oscillator, e.g. 96 MHz, and one IC, the SX, which will comfortably
drive the cable. The SX-28 cost about $5.50 in onesies last time I acquired
some.

Yes, it's a really COOL idea, particularly with this particular CPLD family,
because the software with which to program them is FREE from their web site,
and you have the choice of doing it while on-line or downloading to your own
computer. Moreover, if you want to compare schematics with someone else,
you can do that if they have the same software, making schematics easy to
exchange.

Dick

----- Original Message -----
From: Chuck McManis <cmcmanis_at_mcmanis.com>
To: <classiccmp_at_classiccmp.org>
Sent: Tuesday, July 04, 2000 12:33 PM
Subject: Re: Tim's own version of the Catweasel/Compaticard/whatever


> First, this is a really cool idea. I am glad someone has taken the time to
> make it real.
>
> At 02:06 PM 7/4/00 -0400, Tim wrote:
> >Chip lineup in my current design:
>
> [bunch of parts]
>
> > 8 MHz crystal clock.
> > 1 62C1024 128K*8 SRAM.
> 1 Xilinx CPLD (XC9572 should more than handle it)
>
> The CPLD comes in a PLCC (44 pin) and thus is "hacker friendly" If you
send
> me a schematic I can generate a bit file for the PLD. Digikey sells these
> for $5.53 in single quantities, if we can get by with fewer logic cells
> then the cheaper one is $3.30 each in single quantities.
>
> >I took some pains in my design to allow things to be sped up for more
> >oversampling at a later date.
>
> The CPLD is supposed to run up to 100Mhz so you should have some
head-room.
> I could do a timing analysis at 16, 20, and 24Mhz and see if anything
falls
> out of spec.
>
> >Anything with a bidirectional parallel port oughta work fine.
>
> This is definitely the way to go, it has become a fairly "universal"
interface.
>
> Point me to the schematics and I'll see if it will fit in the smallest
CPLD.
>
> --Chuck
>
>
>
Received on Tue Jul 04 2000 - 14:51:07 BST