MITS 2SIO serial chip?

From: Richard Erlacher <edick_at_idcomm.com>
Date: Mon Dec 17 07:10:27 2001

OK ... I missed that somewhere along the way.

Dick

----- Original Message -----
From: "Ben Franchuk" <bfranchuk_at_jetnet.ab.ca>
To: <classiccmp_at_classiccmp.org>
Sent: Sunday, December 16, 2001 7:37 PM
Subject: Re: MITS 2SIO serial chip?


> Richard Erlacher wrote:
> >
> > Just how does the FPGA fit in here?
> >
> > With a 179x and a 9229, you need only a pal and an oscillator. With a 2797
and
> > no need for data rate changes, i.e. 500 KHz only and MFM only, you only need
the
> > 2 MHz oscillator for the 2797 and an address decoder with which to generate
the
> > select. You may want some logic to generate the wait-states, else your CPU
may
> > not make it around the horn, so to speak, in a loop that gets in sync and
then
> > stays there at 2 microseconds per bit.
> >
> > What goes in the FPGA?
> The CPU of course. Most of the last bit of fidgeting has been getting
> the wait states just right. This is a 12/24 bit cpu that has a strong
> PDP-8/6809/2901 bitslice influence.The cpu design is a 'what if
> scenario' based on a fictional TTL computer of the late 1970's. Version
> #1 of the FPGA 1.5 Mhz? - 74LS381-74LS382 ALU, 74189 RAM - auto boot
> from paper tape?. Not quite sure when 74LS381's came out.
> Version #2 of the FPGA - Monolithic chip - 3.0 Mhz -better timing -
> refresh logic - 40 pin dip - boot from PROM?
> About 50% of the FPGA is data path (24 bits). 25% control - 43 states.
> 25% uart and glue. It all just fits in a Altera 10K10 84 pin PLCC -- 576
> logic cells.
> At the moment I am using a FPGA prototype board with 32KB of static ram
> and
> a Maxim buffer for the serial port in the FPGA. A few leds and switches
> remain from
> debuging the CPU and memory. A old PC is used for program development
> and I/O to the
> prototype board.
> --
> Ben Franchuk --- Pre-historic Cpu's --
> www.jetnet.ab.ca/users/bfranchuk/index.html
>
>
Received on Mon Dec 17 2001 - 07:10:27 GMT