MITS 2SIO serial chip?

From: Allison <ajp166_at_bellatlantic.net>
Date: Mon Dec 17 07:39:14 2001

From: Richard Erlacher <edick_at_idcomm.com>
>would have worked out. I think it might have given the Z80 and edge.
Coming up
>with a fair and general test might be difficult.


I'd liken 6502 VS z80 as one of those depends on what you like things.
Both have stood the test of time far better than many others.

>The Z80 itself wasn't a bad CPU, but the peripheral set they built for it,
with
>its compromises in favor of the mode-2 interrupts meant that you couldn't
use
>wait-states on I/O cycles or on device chip selects to adjust the CPU to
the


I agree, most designers did too. Look at most Z80 designs out there and it
was Z80 with NON-Zilog peripherals. Mode 2 with a little external glue to
use
with non zilog was a very potent config.

>slower peripherals because it had to be looking over the CPU's shoulder to
catch
>the interrupt acknowledge and the RETI instruction. I've recently worked
this
>out by switching the clock rate during I/O and during a pending or current
>interrupt, but it's still a PAIN! What's more, it seems to require more
than
>just a PAL. Handshake logic from a 4-bit wide FIFO (16 pins) seems to be
the
>tool for keeping track of interrupts and their dismissal.


:) Me, I dont use slow Zilog peripherals. The last time I used Zilog IO it
was
the 5330 SCC that ran comfortably at 10mhz with it's own DMA. A TTL
implementation of the mode 2 interrupts made for a nice system as it could
run fast, though I never bothered with RETI, as that not required and adds
much to the logic load.

Allison
Received on Mon Dec 17 2001 - 07:39:14 GMT