Allison wrote:
>
> From: Ben Franchuk <bfranchuk_at_jetnet.ab.ca>
> Right on very few if any! Most went to byte wide or multiples of byte
> wide...
> give a guess why?
4 bit TTL? IBM-360's? ASCII ?
0044 * STILL I AM GLAD WE ARE NOT USING OLD FASHIONED
0046 * PUNCHED CARDS AS IBM WOULD STILL HAVE US DO
0048 * EVEN TODAY IF THE PEE-CEE HAD NOT CAME OUT =)
> I've always felt that 24bvits was a good starting point
> for a clean slate machine or a stretched PDP-8. By Stretched 8 I mean
> just add 12 bits to the right and extend everything else the same amount,
> gives you a 500k page address and a 16mb machine address. So what
> if the instruction set is thin if done with modern FPGAs an easy 100ns
> (12x faster) instruction cycle time would be fine.
If you don't keep ISZ and I/O instructions the same speed that
seems quite possible. The PDP-X runs at 8 MHZ and executes 1 memory
cycle every 500 ns.
http://surfin.spies.com/~dgc/pdp8x/ That is 3x
faster than a PDP-8/I with PDP timing.
> At 48 bits it gets better as then your not horozontal encoding.
> Also if you use a prom to do the opcode to microaddress translation
> it looks nicer and cuts a lot out. Also using the 2901 registers for
> the PC and all saves a bit too. Still, as you noticed a lof of storage
> bits for managing traffic are incurred. A combinational state machine
> is simpler in some respects but far less flexible when it comes to
> fixing a bent opcode.
Bent opcode ... that is where you use the BIG HAMMER!
In the design I was prototyping I had a lot of short instructions thus
a 512x32? rom was more than ample.
--
Ben Franchuk --- Pre-historic Cpu's --
www.jetnet.ab.ca/users/bfranchuk/index.html
Received on Tue Dec 18 2001 - 15:45:48 GMT