MITS 2SIO serial chip?

From: Richard Erlacher <edick_at_idcomm.com>
Date: Thu Dec 20 23:40:21 2001

----- Original Message -----
From: "Ben Franchuk" <bfranchuk_at_jetnet.ab.ca>
To: <classiccmp_at_classiccmp.org>
Sent: Wednesday, December 19, 2001 8:18 PM
Subject: Re: MITS 2SIO serial chip?


> Richard Erlacher wrote:
> >
> > If you run a 20 MHz Z80 against a 20 MHz 6502, you'll find the 6502 performs
WAY
<snip>
> > memory at an average of 200 ns per cycle, while the 6502 does it a 100 ns
rate.
>
> What happens if you look at the M1 cycle as 2 Z80 memory cycles (2 wait
> states).
It's not two memory cycles, is it? How are you interpreting that? There are
TWO problems with it, where fairness to the Z80 is concerned. (1) the M1 is a
very short cycle that occurs somewhat infrequently, and (2) it carries with it
as baggage, the refresh cycle which tme is required to decode the opcode once
it's fetched. This makes the process longer than the normal memory reference
cycle.

If you want a realistic comparison between the to CPU's you have to decide
whether you want to incorporate the benefit of the refresh cycle into the mix,
since it is irrelevant with SRAMs. If, however, you want to incorporate that
refresh cycle as a benefit with some cost, rather than just a cost, then you
have to make decisions as though you were using DRAMs. DRAMs have a cycle time
and an access time. Back in the days of the Z80 and 6502, the shortest cycle
times were on the order of 375 ns. That means that you'd have to have a way to
stretch (ostensibly with wait-states) the M1 to a >375 ns length and
subsequently stretch the REFRESH cycle to that length as well, prior to
executing the next memory reference cycle. There are numerous imaginative ways
to do that, however, and they should be taken into account. Likewise, the same
upper limit on CPU cycle length should be imposed if you're going to compare
with the 6502. A 375 ns cycle length for the 6502 simply means 2.66 MHz clock
rate. If you insert two waits for the Z80's M1, and stretch the clock to force
a >375 NS cycle for refresh, and then pick a clock that will also hit that mark
with a standard unmodified memory reference cycle, you'll be running the Z80 at
~6 MHz

> Now memory speed is the same for both but the clock rateis not.

This is quite incomplete, in terms of levelling the playing field, but it is a
step in that direction.

Dick

> --
> Ben Franchuk --- Pre-historic Cpu's --
> www.jetnet.ab.ca/users/bfranchuk/index.html
>
>
Received on Thu Dec 20 2001 - 23:40:21 GMT