ajp166 wrote:
[snip]
> Parity can only be calculated (simple combinational logic with attendant
> delays) at the time of a wirte so the write must for a given ram speed
> take longer. So if you want the parity to fit in a given memory write
> cycle time you must use faster ram.
For a certain class of processor-memory interface architecture this is
clearly true, but it's hardly a required consequence of using parity or
ECC memory. This is frequently evident in pipelined and particularly
superscalar machines where the processor's bus interface unit runs
asynchronous from the pipes; since the transfers are often in slugs
which are multiples of the machine's wordsize there's usually ample
time to be found to compute parity or ECC polynomials without
stalling or slipping the pipes.
Depending on the processor architecure, I suppose you could also
bury the logic in the memory controller, a la DG.
-ck
--
Chris Kennedy
chris_at_mainecoon.com
http://www.mainecoon.com
PGP fingerprint: 4E99 10B6 7253 B048 6685 6CBC 55E1 20A3 108D AB97
Received on Sat Jan 27 2001 - 17:31:14 GMT