Lack of robustness with 1K and 4K RAM chips (was Re: 2116 and other old memory chips)

From: Richard Erlacher <edick_at_idcomm.com>
Date: Sat Jul 7 02:16:53 2001

see below, plz.

Dick

----- Original Message -----
From: "Ethan Dicks" <ethan_dicks_at_yahoo.com>
To: <classiccmp_at_classiccmp.org>
Sent: Friday, July 06, 2001 11:43 PM
Subject: Re: Lack of robustness with 1K and 4K RAM chips (was Re: 2116 and other
old memory chips)


> --- Richard Erlacher <edick_at_idcomm.com> wrote:
> > > The first COMBOARD used 2114 SRAMs because they were more reliable than
<snip>
>
> This is slightly before my time, but I was told that the earliest 68000
> designs that used DRAMS, used a derivative of the Z-80 scheme because
> the designers of the time were used to it. I didn't mean to imply that
> the 68K had some kind of magical in-built DRAM refresh support.
>
It would have been difficult for them to do, since the CPU didn't have that
capability. The Z80 had a hardware refresh cycle built into its operating
circuitry. It had a refresh counter (though only 7 bits) which was placed on
the address bus while the CPU decoded an opcode.
>
> The microcode faults I was told about for the XC68000 (not MC68000) would
>
The XC68000 was the designator for the earliest units, primarily engineering
samples of the various masks, though mine, (1978-79) from an early mask design
later obsoleted, were marked with the MC68000 designation and a mask number.
One of these had bus timing spec's that allowed it to operate at speeds
exceeding those of later masks at nearly twice the clock rate.
>
> lock things up tight for dozens of clock cycles, then go right back at it,
> as it nothing ever happened. It was strictly internal to the CPU and caused
> by bugs in the first run. Your software never knew what hit it unless it
> was checking timings against an external clock.
>
Anything's possible, but MOT didn't publish anything about this feature in the
various engineering notes the published to characterize the various masks they
produced. Since the original plans were to use the MC68K with cache, support
for DRAM refresh would probably have gotten in the way. Within months of the
release of the 68K, 64K DRAMs that worked as fast as the MC68K could digest the
data became available, and, as the decision had been made to abandon the masks
with timing capable of exceeding the timing for those devices, cacheless
DRAM-based memory systems could be designed to run at full speed.

> By the time I personally touched a 68000, these kinks were long worked out
> (except for knowing that one needs to put low-ohmage resistors (30-60 Ohms)
> in series with the refresh lines from a DRAM controller when attempting
> to refresh several dozen DRAMs (4164s in this case). I chuckled when I
> saw those same resistors in the front memory cartridge of an Amiga 1000.
> They at least got them in there by the time their production started. I
> added hundreds of 68 Ohm resistors to the first production run of COMBOARD-II
> rev 0s. Once one of those came back from the soldering house, I think it
> took 3 hours of bench time to apply all the ECOs. Good thing they were
> already expensive.
>
> -ethan
>
>
>
>
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Received on Sat Jul 07 2001 - 02:16:53 BST

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