CPU design at the gate level

From: Greg Ewing <greg_at_cosc.canterbury.ac.nz>
Date: Mon Nov 5 22:22:59 2001

ajp166 <ajp166_at_bellatlantic.net>:

> Whats
> problemtic is that the ALU must do about 8-16 different operations
> so that would be at least a 512kN part or larger.

Not that big, surely? 4 A inputs, 4 B inputs, carry input,
4 function select inputs comes to 13 inputs, so 8KxN
should be enough.

Greg Ewing, Computer Science Dept, +--------------------------------------+
University of Canterbury, | A citizen of NewZealandCorp, a |
Christchurch, New Zealand | wholly-owned subsidiary of USA Inc. |
greg_at_cosc.canterbury.ac.nz +--------------------------------------+
Received on Mon Nov 05 2001 - 22:22:59 GMT

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