CPU design at the gate level

From: ajp166 <ajp166_at_bellatlantic.net>
Date: Wed Oct 31 20:31:55 2001

The fake for that using discretes is one transistor per emitter used
with the bases and collectors as common. The other is diodes.

The real problem is level shifting and the use of excess redundant


-----Original Message-----
From: Greg Ewing <greg_at_cosc.canterbury.ac.nz>
To: classiccmp_at_classiccmp.org <classiccmp_at_classiccmp.org>
Date: Wednesday, October 31, 2001 8:04 PM
Subject: Re: CPU design at the gate level

>"Peter C. Wallace" <pcw_at_mesanet.com>:
>> There was non-integrated RTL and DTL logic before ICs not sure about
>> integrated TTL...
>I don't think non-integrated TTL is even possible using
>standard parts. It relies on multiple-emitter transistors,
>and I've never heard of anyone making those available
>Greg Ewing, Computer Science Dept,
>University of Canterbury, | A citizen of NewZealandCorp, a |
>Christchurch, New Zealand | wholly-owned subsidiary of USA Inc. |
>greg_at_cosc.canterbury.ac.nz +--------------------------------------+
Received on Wed Oct 31 2001 - 20:31:55 GMT

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