DG MVs (was RE: microcoding a PC into a PDP-11 (was: RE: Classic Computers

From: Chris Kennedy <chris_at_mainecoon.com>
Date: Tue Sep 25 09:42:36 2001

Derek Peschel wrote:

> ... And once you've loaded your own microcode, do the PROMs take up any
> room in the microaddress space? And does the microcode handle the load
> operation, or is there some sort of dedicated circuit?

I can't find any _architectural_ specification for this. The PROMs clearly
do not form part of the MV microcode set; in effect a bank switch takes
place after the microcode is loaded.

> I assume the load operation isn't supposed to happen while an ordinary
> program is running (though that _would_ be an opportunity for spectacularly
> efficient and inscrutable code).

There's no functionality in the MV instruction set that allows the
control store to be manipulated -- it's implemented in the dorked-up
Nova 800 instruction set in the tried-and-true fashion of the
16-bit Eclipse instruction set: Recycle meaningless-but-
valid instructions (for example, things like register-to-register
moves with the same source and destination register with no skip
or always skip conditions set) to create space for the new instruction.

> It's scary how similar this is to a popular booting technique (switch on
> boot ROM, use it to load RAM, switch off boot ROM) except, of course, that
> you're one level lower.

It was modestly brilliant. By creating a hardwired ISA using a model
that was well understood (i.e., unlikely to ever need revision), the
designers allowed themselves a much higher level of abstraction when
building code that had to, among other things, interact with the
I/O subsystem. Since they already had architectural verification
programs in place for the Nova it was trivial to modify them to
verify the correctness of the boot firmware.

Chris Kennedy
PGP fingerprint: 4E99 10B6 7253 B048 6685  6CBC 55E1 20A3 108D AB97
Received on Tue Sep 25 2001 - 09:42:36 BST

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