While browsing sites for 6800 information, I came across this quote from
<
http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?Mostec>.
which talks about the design goals for the 650x in comparison to the 6800.
>The design goal was a low-cost (smaler chip) design, realized by
simplifying the decoder stage. There were no instructions with the value
xxxxxx11, reducing the 1-of-4 decoder to a single NAND gate. Instructions
with the value xxxxxx11 actually executed two instructions in paralell, some
of them useful. <
Now, I didn't look at an opcode map, but it seems that this is an
interesting twist that I've never seen quoted when people discussed the
mysterious undocumented 6502 opcodes executing what appeared to be multiple
instructions.
Any thoughts?
Rich
==========================
Richard A. Cini, Jr.
Congress Financial Corporation
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30th Floor
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(212) 545-4402
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Received on Thu Jun 06 2002 - 14:56:03 BST