[CCTECH] Interesting tidbit on 6502

From: Richard Erlacher <edick_at_idcomm.com>
Date: Thu Jun 6 17:14:18 2002

One of the more interesting features of the 6502 is that when you're looking
at the data bus, it shows you what last was on the bus in those cases where
there's nothing present to drive the data-in bus. This will give you
information useful in figuring out what is going inside the chip, and, that's
what gave me the clues that convinced me that the reason the 6502 is so cheap
on silicon is that it doesn't use counters for its registers, but, rather,
uses simple gated latches and uses the ALU to operate on the addresses during
phase-2 while operating on the data during phase-1.

If you look at what's required to build a synchronous counter large enough to
support the simple register set in the 6502 you'll see that the saved gates
are sufficient to warrant its design in exactly that way, and that it would
yield a significant savings in silicon. It allows you to use a relatively
complex ALU, together with a register set that's essentially a small RAM array
with an instruction set that never operates on two registers in a single
cycle. If you build the PC, the address bus registers, the SP, the two index
registers, and the accumulator as 8-bit registers, it's easy to see why one
would do things that way. I'm not sure anybody has ever taken a really close
look at what happens when each possible opcode is fed to the 6502 as the first
instruction after a reset and then recorded what the CPU does with it right up
to the next SYNC, signalling that a new opcode is being fetched, but it might
be a useful extension on what's been done. Of course, the 6502 is of little
interest to persons planning any practical endeavors, so this fits squarely
under the aegis of this forum.

Dick

----- Original Message -----
From: "Cini, Richard" <RCini_at_congressfinancial.com>
To: "'CCLTech'" <cctech_at_classiccmp.org>
Sent: Thursday, June 06, 2002 1:56 PM
Subject: [CCTECH] Interesting tidbit on 6502


> While browsing sites for 6800 information, I came across this quote from
> <http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?Mostec>.
> which talks about the design goals for the 650x in comparison to the 6800.
>
> >The design goal was a low-cost (smaler chip) design, realized by
> simplifying the decoder stage. There were no instructions with the value
> xxxxxx11, reducing the 1-of-4 decoder to a single NAND gate. Instructions
> with the value xxxxxx11 actually executed two instructions in paralell, some
> of them useful. <
> Now, I didn't look at an opcode map, but it seems that this is an
> interesting twist that I've never seen quoted when people discussed the
> mysterious undocumented 6502 opcodes executing what appeared to be multiple
> instructions.
> Any thoughts?
> Rich
>
> ==========================
> Richard A. Cini, Jr.
> Congress Financial Corporation
> 1133 Avenue of the Americas
> 30th Floor
> New York, NY 10036
> (212) 545-4402
> (212) 840-6259 (facsimile)
>
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Received on Thu Jun 06 2002 - 17:14:18 BST

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