6502 cycles and subtleties (was Re: Assembly on a Apple IIc+)

From: Eric Smith <eric_at_brouhaha.com>
Date: Sat Feb 8 19:02:01 2003

Pete wrote about my example of the 6502 ADC immediate instruction
being pipelined:
> True. Most instructions don't work like that, though.

Well, I haven't counted them, but pretty much all instructions that
use the ALU do that. This includes ADC, SBC, ORA, AND, EOR, BIT,
and (when the accumulator is the destination) LSL, ASR, ROR, and ROL.
And the PLP and PLA instructions, which increment the stack pointer
using the ALU during the next fetch. Probably others that don't come to
mind at the moment, as well.

The original claim back in 1975 that the 6502 (and fmaily) was pipelined
was probably intended as a comparison to the other microprocessors of
the time, especially the somewhat similar 6800, which took more clock
cycles to do most operations, because it did not have even the small amount
of pipelining of the 6502.
Received on Sat Feb 08 2003 - 19:02:01 GMT

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