On Feb 8, 11:41, Eric Smith wrote:
> Pete wrote:
> > You must be thinking of some different 6502 to the rest of us :-)
As
> > Sellam said, no 6502 opcode takes less than two clock cycles to
> > execute, and most take more (up to 7): the only 2-cycle
instructions are
> > the ones with implied addressing, like RTS, CLI, TAX, ...
>
> Not RTS, that takes a bunch.
Oops, wrong column! Yes, it takes 6.
> There is a little bit of pipelining internally, but it's not really
> obvious. The last ALU operation of an instruction is generally done
> during the same clock cycle as the fetch of the next instruction.
> For instance, when you do an "ADC #35" instruction (add with carry
> immediate), it's a two-cycle instruction, but it really takes three
> cycles to complete -- the third cycle is overlapped with the
following
> instruction's fetch. During the first cycle the opcode is fetched,
> during the second cycle the immediate operand is fetched, and during
the
> third cycle, which is the first cycle of the next instruction, the
actual
> add occurs.
True. Most instructions don't work like that, though.
> > There aren't two CPU cycles per clock cycle. Perhaps you're
thinking of
> > the fact that the 6502 uses a two-phase clock, and does part of the
CPU
> > cycle during phi-1, and part during phi-2?
>
> Perhaps the original poster thought that, but it's just the old
standard
> two-phase NMOS logic. It takes two phases to do just about anything
> internally, so it's not a matter of doing two things sequentially in
> one clock cycle. (A small number of things occur in parallel in some
> cycles, though.)
Yes, *I* know that, but I don't think Jim did :-)
--
Pete Peter Turnbull
Network Manager
University of York
Received on Sat Feb 08 2003 - 17:11:00 GMT