Synertek 6507

From: Tony Duell <ard_at_p850ug1.demon.co.uk>
Date: Thu Mar 13 19:25:00 2003

> >According to my 1983 Synertek book, the SY6507 _is_ a 28-pin 65xx CPU with
> >8K addressing. The only video controllers they list are the SY6545, SY6845,
> >SY66450 and SY66550.
> >
>
> Hi Jim
> This is what Eric Smith tells me as well. As I told

And it's waht I suspect too...

> him, it doesn't make much sense. The board has a 6502
> as well as the 6507 with the data lines tied together.
> I guess they could use opposite phases or something.

Indeed. That was a very common trick to have 2 650x CPUs in parallel.
It's how the CBM IEEE-488 disk drives were designed, for example. You
need a mux on the address lines (because the CPU does not tri-state those
between memory accesses), but you can tie the data lines together.

> I was tracing down the sync signals for the video
> and they seem to be coming from this part??

Think of the 6507 as (very) programmable counter chain (in the simplest
case just have it executing NOPs and JMPs). That's the video address
logic. And you could probably get it to pulse the high-order address
lines (by jumping up there and back again) to generate sync signals.

I once had this idea (which I've never followed up) to use a common,
fast, 8 bit processor with no instruction pipelining (so you know what
the buses are doing and when) as a microcode sequencer. Just give it 8+n
bit wide memory, with the 8 bits consisting of NOPs and (conditional)
jumps. the n bits are the control lines to whatever you're microcoding.

-tony
Received on Thu Mar 13 2003 - 19:25:00 GMT