q about PDP11/34 schematics (clock generation)

From: Bert Thomas <bert_at_brothom.nl>
Date: Sun Dec 26 06:42:18 2004

Hi all,

Can anyone explain to me how the clock generation of the PDP11/34 works?
I see in the schematics on page 1-5 that clock signals are "generated"
(?) by a delay line. That is: the component is referenced as E104 and
the parts list mentions it as "delay line 150nS" As I don't have any
other info on this part, I'd like to find out how this component works.
Appearantly there are multiple signals coming from this device.

Please forgive me my ignorance, I think I might be to young to know


Received on Sun Dec 26 2004 - 06:42:18 GMT

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