q about PDP11/34 schematics (clock generation)

From: Tony Duell <ard_at_p850ug1.demon.co.uk>
Date: Sun Dec 26 08:45:49 2004

> Hi all,
> Can anyone explain to me how the clock generation of the PDP11/34 works?
> I see in the schematics on page 1-5 that clock signals are "generated"
> (?) by a delay line. That is: the component is referenced as E104 and
> the parts list mentions it as "delay line 150nS" As I don't have any
> other info on this part, I'd like to find out how this component works.
> Appearantly there are multiple signals coming from this device.

I don't have the 11/34 schematics to hand (I can get them out if need
be), but I can give some general comments.

A delay line is what the name implies. A component that delays a signal,
here a digital signal. If the input changes, then the output changes a
certain time (here 150ns) later.

The reason for multiple outputs (often called 'taps' is that you can get
signals delayed by different amounts. A 150ns delay line may have 5 taps,
say, 30ns apart. If the input changes, the first tap changes after
30ns,the next after 60ns, etc.

Typicaly, you make an oscillator from a delay line by invertiong the
output and feeding it back to the input (the 11/34 may well be a lot more
complicated than this, there may be circuity to halt the clock under
certain conditions).

Suppose the input to the delay line was 0, and has just gone to 1. The
output remains 0 for the next 150ns (since that's the delay time), then
goes to 1 also. So after 150ns, the output goes to one, that's inverted,
and so the input goes to 0. After another 150ns, the output goes to 0,
that's inverted,. and the input goes to 1. Then the cycle repeats. You
have a nscillator with a period of about 300ns.

Received on Sun Dec 26 2004 - 08:45:49 GMT

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