> Paul Koning wrote:
>
> But the real issue is that NO ONE will tell you the internals of their
> FPGA, so you can't figure out the bit patterns that you need to
> perform a given logic function. Too bad really, because the logic
> synthesis software available from the chip vendors often sucks pretty
> badly. I have a bunch of battle scars coping with really stupid bugs
> in Lattice tools, which will not be fixed since they are apparently
> considered normal behavior.
>
> I think if you have infinite pull the situation is sometimes better --
> I've seen some evidence that DEC was able to get Xilinx to tell it how
> to synthesize for those chips. And they did it much better... but
> those were research tools in the Palo Alto group only.
>
Oh, they do tell you, but for a substantial fee, and an NDA to go with
that, just to make shure they can sue your pants off when you happen to
spill the secret... :)
There is rumor of a Verilog simulator/synthesiser that speaks Xilinx.
I have not yet tried it but here is the link:
http://www.icarus.com/eda/verilog/
It is for free and as such it might suck, but at least it do that for
a moderate fee.
Have fun.
/Ulf A.
Received on Sun Mar 21 2004 - 15:09:42 GMT